公开(公告)号：US20170317162A1

公开(公告)日：2017-11-02

申请号：US15518616

申请日：2015-12-11

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Shinya NISHIMURA ,  Hirokazu FUJIWARA ,  Narumasa SOEJIMA ,  Yuichi TAKEUCHI

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/063 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A semiconductor device includes a p-type semiconductor region in contact with a bottom face of a trench gate, wherein the p-type semiconductor region includes a first p-type semiconductor region containing a first type of p-type impurities and a second p-type semiconductor region containing a second type of p-type impurities. The first p-type semiconductor region is located between the trench gate and the second p-type semiconductor region. In a view along the depth direction, the second p-type semiconductor region is located within a part of the first p-type semiconductor region. A diffusion coefficient of the second type of p-type impurities is smaller than a diffusion coefficient of the first type of p-type impurities.

公开(公告)号：US20170084735A1

公开(公告)日：2017-03-23

申请号：US15365150

申请日：2016-11-30

Applicant: Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi TAKEUCHI ,  Naohiro SUZUKI ,  Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  Narumasa SOEJIMA ,  Yukihiko WATANABE

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L21/04 ,  H01L29/66 ,  H01L29/417 ,  H01L29/872 ,  H01L29/15 ,  H01L21/761

CPC classification number: H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

公开(公告)号：US20190067420A1

公开(公告)日：2019-02-28

申请号：US16027825

申请日：2018-07-05

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Hidefumi TAKAYA ,  Yasushi URAKAMI ,  Narumasa SOEJIMA

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739 ,  H01L29/06

Abstract: A semiconductor device may be provided with a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode provided within a trench via a gate insulator film. The semiconductor substrate may include a p-type body layer being in contact with the upper electrode, an n-type drift layer intervening between the body layer and the lower electrode, a p-type floating region provided along a bottom surface of the trench, and a p-type connection region extending between the body layer and the floating region along a side surface of the trench. The trench may include a first section where the connection region is not provided and a second section where the connection region is provided. An inclination angle of the side surface of the trench in the second section may be greater than an inclination angle of the side surface of the trench in the first section.

公开(公告)号：US20180144938A1

公开(公告)日：2018-05-24

申请号：US15726603

申请日：2017-10-06

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Norihiro TOGAWA ,  Narumasa SOEJIMA ,  Shoji MIZUNO

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/872

CPC classification number: H01L21/0495 ,  H01L21/046 ,  H01L21/26506 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66143 ,  H01L29/872

Abstract: A method of manufacturing a semiconductor device is provided with: implanting charged particles including oxygen into a surface of a SiC wafer; and forming a Schottky electrode that makes Schottky contact with the SiC wafer on the surface after the implantation of the charged particles.

公开(公告)号：US20140353683A1

公开(公告)日：2014-12-04

申请号：US14287585

申请日：2014-05-27

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Hisashi ISHIMABUSHI ,  Tomohiro MIMURA ,  Narumasa SOEJIMA

IPC: H01L21/265 ,  H01L29/16

CPC classification number: H01L29/1608 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/6606 ,  H01L29/7802 ,  H01L29/78642 ,  H01L29/861 ,  H01L29/872

Abstract: In a semiconductor substrate preparation step, a semiconductor substrate which is made of SiC and in which a first semiconductor region of a first conductivity type is formed is prepared. In a second semiconductor region forming step, a second semiconductor region is formed by implanting an impurity of a second conductivity type into a first semiconductor region through multiple ion implantation steps while varying implantation depths of the respective multiple ion implantation steps. In the second semiconductor region forming step, a dose amount of the impurity when an implantation energy of multiple ion implantation steps is the largest is smaller than a dose amount of impurity when the implantation energy is not the largest.

Abstract translation: 在半导体衬底制备步骤中，制备由SiC制成并且其中形成第一导电类型的第一半导体区域的半导体衬底。 在第二半导体区域形成步骤中，通过在改变多个离子注入步骤的注入深度的同时通过多个离子注入步骤将第二导电类型的杂质注入到第一半导体区域中形成第二半导体区域。 在第二半导体区域形成步骤中，当多个离子注入步骤的注入能量最大时，杂质的剂量量小于当注入能量不是最大时的杂质的剂量。

公开(公告)号：US20180097061A1

公开(公告)日：2018-04-05

申请号：US15560662

申请日：2016-03-10

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Tomohiro MIMURA ,  Takashi KANEMURA ,  Masahiro SUGIMOTO ,  Narumasa SOEJIMA

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/105 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/0856 ,  H01L29/1095 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7813

Abstract: A semiconductor device includes: a drain region; a drift layer made of a first conductivity type semiconductor with lower impurity concentration than the drain region; a base region made of a second conductivity type semiconductor; a source region made of the first conductivity type semiconductor with higher concentration; a contact region made of the second conductivity type semiconductor with higher concentration; a trench structure having a first gate insulation film and a first gate electrode arranged at an opening side of the trench and to be deeper than the base region, and a bottom part insulation film; a source electrode electrically connected to the source and contact regions; and a drain electrode at a rear side of the drain region. The drain is arranged to be deeper than the base region. The first gate insulation film is made of higher dielectric insulation material than the bottom part insulation film.

公开(公告)号：US20180145144A1

公开(公告)日：2018-05-24

申请号：US15784877

申请日：2017-10-16

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Teruaki KUMAZAWA ,  Narumasa SOEJIMA ,  Yuichi TAKEUCHI

IPC: H01L29/47 ,  H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L21/285

CPC classification number: H01L29/47 ,  H01L21/0465 ,  H01L21/0495 ,  H01L21/28537 ,  H01L21/28581 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66143 ,  H01L29/872

Abstract: A method of manufacturing a semiconductor device includes: setting a plurality of main semiconductor wafers and a plurality of sub semiconductor wafers in a load lock chamber of an electrode forming equipment; repeating a wafer-transfer and electrode-formation process of transferring at least one of the main semiconductor wafers from the load lock chamber to the film formation chamber in a state where the load lock chamber and the film formation chamber are decompressed and then forming a surface electrode on a surface of the at least one main semiconductor wafer transferred in the film formation chamber; removing the main semiconductor wafers on which the surface electrodes have been formed and the sub semiconductor wafers from the electrode forming equipment without forming an electrode on the sub semiconductor wafers by the electrode forming equipment; and making the surface electrodes Schottky-contact the main semiconductor wafers.

公开(公告)号：US20180090612A1

公开(公告)日：2018-03-29

申请号：US15664379

申请日：2017-07-31

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Hirokazu FUJIWARA ,  Yuichi TAKEUCHI ,  Narumasa SOEJIMA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/423 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66704 ,  H01L29/66734 ,  H01L29/7825

Abstract: A switching device includes a semiconductor substrate; a trench; a conductor layer extending in a longitudinal direction of the trench so as to be in contact with a bottom surface of the trench; a bottom insulating layer covering an upper surface of the conductor layer; a gate insulating layer covering a side surface of the trench; and a gate electrode disposed in the trench. The semiconductor substrate includes a first semiconductor region of a first conductivity type, a body region of a second conductivity type, a second semiconductor region of the first conductivity type, a bottom semiconductor region of the second conductivity type extending in the longitudinal direction so as to be in contact with the conductor layer, and a connection semiconductor region of the second conductivity type connected to the body region and to the bottom semiconductor region.

公开(公告)号：US20170018643A1

公开(公告)日：2017-01-19

申请号：US15124326

申请日：2015-02-10

Applicant: Toyota Jidosha Kabushiki Kaisha ,  Denso Corporation

Inventor： Hidefumi TAKAYA ,  Jun SAITO ,  Akitaka SOENO ,  Toshimasa YAMAMOTO ,  Narumasa SOEJIMA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L21/761 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7811 ,  H01L21/761 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/12 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device provided herein includes: a fourth region of a p-type being in contact with a lower end of the gate trench; a termination trench provided in the front surface in a range outside the second region; a lower end p-type region of the p-type being in contact with a lower end of the termination trench; a lateral p-type region of the p-type being in contact with a lateral surface of the termination trench on an outer circumferential side, connected to the lower end p-type region, and exposed on the front surface; and a plurality of guard ring regions provided on the outer circumferential side with respect to the lateral p-type region and exposed on the front surface.

Abstract translation: 本文提供的半导体器件包括：p型的第四区域与栅极沟槽的下端接触; 在第二区域外的范围内设置在前表面的终端沟槽; p型的下端p型区域与端接沟槽的下端接触; p型侧面p型区域与外周侧的终端沟槽的侧面接触，与下端p型区域连接并露出在前表面上; 以及相对于侧面p型区域在外周侧设置并暴露在前表面上的多个保护环区域。