公开(公告)号：US20180097063A1

公开(公告)日：2018-04-05

申请号：US15719607

申请日：2017-09-29

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hideaki MATSUYAMA ,  Shinya TAKASHIMA ,  Katsunori UENO ,  Takuro INAMOTO ,  Masaharu EDO

IPC分类号： H01L29/10 ,  H01L29/20 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L29/66

CPC分类号： H01L29/1095 ,  H01L21/0254 ,  H01L21/26546 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/66734 ,  H01L29/7813

摘要： In a case where a semiconductor layer is epitaxially grown on a step shape formed due to CBL (current blocking layer) formation, the crystallinity of the semiconductor layer lowers. Also, a GaN layer that is epitaxially regrown on the CBL is not formed continuously by epitaxial growth, and therefore the crystallinity of the GaN layer lowers. A vertical semiconductor device manufacturing method is provided that comprises: a step of epitaxially growing a gallium nitride-based n-type semiconductor layer on a gallium nitride-based semiconductor substrate; a step of epitaxially growing a gallium nitride-based p-type semiconductor layer on the n-type semiconductor layer; and a step of ion-implanting p-type impurities to form a p+-type embedded region selectively in a predetermined depth range across the boundary between the n-type semiconductor layer and the p-type semiconductor layer.

公开(公告)号：US20180019129A1

公开(公告)日：2018-01-18

申请号：US15609040

申请日：2017-05-31

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hideaki MATSUYAMA

IPC分类号： H01L21/225 ,  H01L29/66

CPC分类号： H01L21/2258 ,  H01L29/66522 ,  H01L29/66666

摘要： There is a problem that even if impurities are made to thermally diffuse in a temperature range of 700° C.-1150° C., a good ohmic contact cannot be formed in a p-type group-III nitride semiconductor layer.Provided is a semiconductor device manufacturing method having a group-III nitride semiconductor substrate and a p-type group-III nitride semiconductor layer on the group-III nitride semiconductor substrate, including forming a magnesium containing layer on and in direct contact with the p-type group-III nitride semiconductor layer; and annealing the p-type group-III nitride semiconductor layer at a temperature more than or equal to 1300° C. to form a p+-type region which contains magnesium as an impurity in the p-type group-III nitride semiconductor layer located immediately below the magnesium containing layer.

公开(公告)号：US20210104607A1

公开(公告)日：2021-04-08

申请号：US17001617

申请日：2020-08-24

申请人： FUJI ELECTRIC CO., LTD.

发明人： Ryo TANAKA ,  Shinya TAKASHIMA ,  Hideaki MATSUYAMA ,  Katsunori UENO ,  Masaharu EDO

IPC分类号： H01L29/20 ,  H01L21/20 ,  H01L21/265 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

摘要： A nitride semiconductor device is provided, comprising: a first nitride semiconductor layer of a first conductivity-type; a second nitride semiconductor layer of a second conductivity-type provided above the first nitride semiconductor layer; a junction region of a first conductivity-type which is provided to extend in a direction from a front surface of the second nitride semiconductor layer to the first nitride semiconductor layer and has a doping concentration NJFET equal to or higher than that of the first nitride semiconductor layer; and a source region of a first conductivity-type which is provided more shallowly than the junction region and has a doping concentration equal to or higher than the doping concentration NJFET, wherein a dopant of the source region is an element with an atomic weight larger than that of a dopant in the junction region.

公开(公告)号：US20190006184A1

公开(公告)日：2019-01-03

申请号：US16021036

申请日：2018-06-28

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hideaki MATSUYAMA ,  Shinya TAKASHIMA ,  Katsunori UENO ,  Ryo TANAKA ,  Masaharu EDO ,  Daisuke MORI ,  Hirotaka SUDA ,  Hideaki TERANISHI ,  Chizuru INOUE

IPC分类号： H01L21/28 ,  H01L29/20 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/423 ,  H01L29/24 ,  H01L29/267

摘要： A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.