公开(公告)号：US20170287780A1

公开(公告)日：2017-10-05

申请号：US15089834

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L21/768 ,  H01L21/28 ,  H01L23/535 ,  H01L27/092 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: One method disclosed includes, among other things, forming a first plurality of gate cavities in a first dielectric layer. A work function material layer is formed in the first plurality of gate cavities. A first conductive material is formed in at least a subset of the first plurality of gate cavities above the work function material layer to define a first plurality of gate structures. A first contact recess is formed in the first dielectric layer between two of the first plurality of gate structures. A second conductive material is formed in the first contact recess. The work function material layer is recessed selectively to the first and second conductive materials to define a plurality of cap recesses. A cap layer is formed in the plurality of cap recesses.

公开(公告)号：US09780192B2

公开(公告)日：2017-10-03

申请号：US15093881

申请日：2016-04-08

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Mahalingam Nandakumar

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/321 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/32

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/7833

Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.

公开(公告)号：US09779947B2

公开(公告)日：2017-10-03

申请号：US14989351

申请日：2016-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jin-Aun Ng ,  Jen-Sheng Yang ,  Pei-Ren Jeng ,  Jung-Hui Kao ,  Shih-Hao Lo ,  Yuan-Tien Tu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang ,  Maxi Chang ,  Chih-Tang Peng ,  Chih-Yang Yeh ,  Ta-Wei Lin ,  Huan-Just Lin ,  Hui-Wen Lin

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28229 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659

Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.

公开(公告)号：US20170278948A1

公开(公告)日：2017-09-28

申请号：US15620241

申请日：2017-06-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Chiung-Han Yeh ,  Lee-Wee Teo ,  Yu-Ying Hsu ,  Bao-Ru Young

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L27/0629 ,  H01L27/0802 ,  H01L27/0922 ,  H01L28/20 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2223/6672

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

公开(公告)号：US20170271481A1

公开(公告)日：2017-09-21

申请号：US15616197

申请日：2017-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. Anderson ,  Bruce B. Doris ,  Seong-Dong Kim ,  Rajasekhar Venigalla

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/11273 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.

公开(公告)号：US09755039B2

公开(公告)日：2017-09-05

申请号：US13192718

申请日：2011-07-28

Applicant: Hsueh Wen Tsau

Inventor： Hsueh Wen Tsau

IPC: H01L21/70 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/51

CPC classification number: H01L29/4983 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: A semiconductor device includes a substrate, a gate dielectric layer on the substrate, and a gate electrode stack on the gate dielectric layer. The gate electrode stack includes a metal filling line, a wetting layer, a metal diffusion blocking layer, and a work function layer. The wetting layer is in contact with a sidewall and a bottom surface of the metal filling line. The metal diffusion blocking layer is in contact with the wetting layer and covers the sidewall and the bottom surface of the metal filling line with the wetting layer therebetween. The work function layer covers the sidewall and the bottom surface of the metal filling line with the wetting layer and the metal diffusion blocking layer therebetween.

公开(公告)号：US09755013B2

公开(公告)日：2017-09-05

申请号：US14692881

申请日：2015-04-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L49/02 ,  H01L27/06 ,  H01L21/8238

CPC classification number: H01L28/92 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0629

Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.

公开(公告)号：US09754841B2

公开(公告)日：2017-09-05

申请号：US15060572

申请日：2016-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

IPC: H01L21/8238 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

公开(公告)号：US20170250117A1

公开(公告)日：2017-08-31

申请号：US15055826

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji KANNAN ,  Unoh KWON ,  Siddarth KRISHNAN ,  Takashi ANDO ,  Vijay NARAYANAN

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/324 ,  H01L21/225

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

Abstract: Semiconductor device fabrication methods are provided which include: providing a structure with at least one region and including a dielectric layer disposed over a substrate; forming a multilayer stack structure including a threshold-voltage adjusting layer over the dielectric layer, the multilayer stack structure including a first threshold-voltage adjusting layer in a first region of the at least one region, and a second threshold-voltage adjusting layer in a second region of the at least one region; and annealing the structure to define a varying threshold voltage of the at least one region, the annealing facilitating diffusion of at least one threshold voltage adjusting species from the first threshold-voltage adjusting layer and the second threshold-voltage adjusting layer into the dielectric layer, where a threshold voltage of the first region is independent of the threshold voltage of the second region.

公开(公告)号：US09748356B2

公开(公告)日：2017-08-29

申请号：US13931234

申请日：2013-06-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/775 ,  H01L21/66 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/45 ,  H01L29/778 ,  H01L29/41 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823842 ,  H01L22/12 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/413 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66431 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7781 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.