公开(公告)号：US20170250117A1

公开(公告)日：2017-08-31

申请号：US15055826

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji KANNAN ,  Unoh KWON ,  Siddarth KRISHNAN ,  Takashi ANDO ,  Vijay NARAYANAN

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/324 ,  H01L21/225

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

Abstract: Semiconductor device fabrication methods are provided which include: providing a structure with at least one region and including a dielectric layer disposed over a substrate; forming a multilayer stack structure including a threshold-voltage adjusting layer over the dielectric layer, the multilayer stack structure including a first threshold-voltage adjusting layer in a first region of the at least one region, and a second threshold-voltage adjusting layer in a second region of the at least one region; and annealing the structure to define a varying threshold voltage of the at least one region, the annealing facilitating diffusion of at least one threshold voltage adjusting species from the first threshold-voltage adjusting layer and the second threshold-voltage adjusting layer into the dielectric layer, where a threshold voltage of the first region is independent of the threshold voltage of the second region.