公开(公告)号：US20230343637A1

公开(公告)日：2023-10-26

申请号：US17660518

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ying-Yu LAI ,  Chih-Yun WANG ,  Chih-Hsuan LIN ,  Hsi Chung CHEN

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/40 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/76814 ,  H01L29/41775 ,  H01L29/401 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/823475 ,  H01L21/31122 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/02063 ,  H01L29/41791 ,  H01L29/42392

Abstract: Multiple dry etching operations are performed to form an opening for an interconnect structure, with a wet cleaning operation performed in between the dry etching operations. This multi-step etch approach increases the effectiveness of residual material removal, which increases the quality of the interconnect structure and reduces the likelihood of under etching, both of which increase semiconductor device yield and semiconductor device performance.

公开(公告)号：US11798940B2

公开(公告)日：2023-10-24

申请号：US16897167

申请日：2020-06-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pin-Dai Sue ,  Tzung-Yo Hung ,  Jung-Hsuan Chen ,  Ting-Wei Chiang

IPC: H01L21/8238 ,  H01L27/088 ,  H01L23/528 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/528 ,  H01L29/66545

Abstract: A semiconductor device includes a first transistor disposed over a substrate, a second disposed over the first transistor, and a conductive trace. The first transistor includes a first active area extending on a first layer. The second transistor includes a second active area extending on a second layer above the first layer. The conductive trace extends on a third layer. The first to third layers are separated from each other in a first direction, and the third layer is interposed between the first and second layers. The first active area, the second active area, and the conductive trace overlap in a layout view.

公开(公告)号：US20230335545A1

公开(公告)日：2023-10-19

申请号：US18341369

申请日：2023-06-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou SIO ,  Chih-Liang CHEN ,  Hui-Ting YANG ,  Shun Li CHEN ,  Ko-Bin KAO ,  Chih-Ming LAI ,  Ru-Gun LIU ,  Charles Chew-Yuen YOUNG

IPC: H01L21/8234 ,  H01L29/417 ,  H01L21/3213 ,  H01L29/423 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L27/0207 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/42376 ,  H10B10/12

Abstract: A method (of manufacturing conductors for a semiconductor device) includes: forming active regions (ARs) in a first layer, the ARs extending in a first direction; forming a conductive layer over the first layer; forming first, second and third caps over the conductive layer, the caps extending in a second direction perpendicular to the first direction, and the caps having corresponding first, second and third sensitivities that are different from each other; removing portions of the conductive layer not under the first, second or third caps resulting in gate electrodes under the first caps and first and second drain/source (D/S) electrodes correspondingly under the second or third caps; and selectively removing portions of corresponding ones of the first D/S electrodes and the second D/S electrodes.

公开(公告)号：US11791335B2

公开(公告)日：2023-10-17

申请号：US17327123

申请日：2021-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te Lin ,  Wei-Yuan Lu ,  Feng-Cheng Yang

IPC: H01L27/088 ,  H01L23/522 ,  H01L23/48 ,  H01L29/06 ,  H01L27/06 ,  H01L29/66 ,  H01L27/11 ,  H01L49/02 ,  H01L21/8234 ,  H10B10/00 ,  H10B61/00 ,  H10N59/00 ,  H01L21/8258

CPC classification number: H01L27/088 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/5226 ,  H01L27/0688 ,  H01L28/40 ,  H01L29/0653 ,  H01L29/66545 ,  H10B10/12 ,  H10B61/00 ,  H10N59/00 ,  H01L21/8258 ,  H01L27/0605

Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.

公开(公告)号：US20230317520A1

公开(公告)日：2023-10-05

申请号：US17712461

申请日：2022-04-04

Applicant: Winbond Electronics Corp.

Inventor： Chun-Hung LIN ,  Kao-Tsair TSAI ,  Chung-Hsien LIU ,  Tz-Hau GUO ,  Yen-Jui CHU

IPC: H01L21/768 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/823475 ,  H01L21/76834

Abstract: A manufacturing method for a semiconductor structure is provided. First active areas, a second active area, and a third active area are formed. A first dielectric layer is formed on the active areas. A patterned region that includes a cavity region and a dielectric region is formed in the first dielectric layer, and the cavity region surrounds the dielectric region. A filling layer is formed in the cavity region. Multiple first contact holes and at least one second contact hole that penetrate the first dielectric layer are formed. Each first contact hole exposes a portion of the corresponding first active area, and the second contact hole replaces the dielectric region and exposes a portion of the second active area. Metal layers are filled in to the first contact holes and the second contact hole.

公开(公告)号：US11776898B2

公开(公告)日：2023-10-03

申请号：US16955722

申请日：2018-02-22

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Anh Phan ,  Gilbert Dewey ,  Willy Rachmady ,  Patrick Morrow

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L23/532 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/768 ,  H01L21/822

CPC classification number: H01L23/5226 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53295 ,  H01L27/0886 ,  H01L29/0638 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/8221 ,  H01L27/0688

Abstract: Interconnect metallization of an integrated circuit device includes a sidewall contact between conductive features. In a stacked device, a terminal interconnect of one device layer may intersect a sidewall of a conductive feature in another device layer or between two devices layers. In some examples, a terminal interconnect coupled to a gate, source, or drain terminal of a finFET in a vertically-stacked device may extend to a depth below a plane of the fin and intersect a sidewall of another interconnect, or another device terminal, that is in another plane of the stacked device. A stop layer below a top surface of the conductive feature may allow for sidewall contact while avoiding interconnect shorts.

公开(公告)号：US11776853B2

公开(公告)日：2023-10-03

申请号：US17646763

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Hao Chen ,  Che-Cheng Chang ,  Horng-Huei Tseng ,  Wen-Tung Chen ,  Yu-Cheng Liu

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/8238 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L21/823431 ,  H01L21/0217 ,  H01L21/02063 ,  H01L21/0273 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/823475 ,  H01L21/02271 ,  H01L21/823481 ,  H01L21/823821 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/013 ,  H01L2924/01013 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/013 ,  H01L2924/01013 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014

Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

公开(公告)号：US11769690B2

公开(公告)日：2023-09-26

申请号：US17464012

申请日：2021-09-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Wai-Yi Lien ,  Yu-Ming Lin

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/28 ,  H01L23/485 ,  H01L29/417

CPC classification number: H01L21/76802 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/785 ,  H01L21/823425 ,  H01L2029/7858

Abstract: A device includes a substrate, a first metal feature over the substrate, first and second spacers, a first dielectric layer, and a second metal feature. The first and second spacers are on opposite sidewalls of the conductive feature, respectively. The first dielectric layer is in contact with the first spacer, in which a top surface of the protection layer is higher than a top surface of the first spacer. The second metal feature is electrically connected to the first metal structure and in contact with a top surface and a sidewall of the protection layer.

公开(公告)号：US20230299167A1

公开(公告)日：2023-09-21

申请号：US18321620

申请日：2023-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Huan-Chieh Su ,  Chun-Yuan Chen ,  Lo-Heng Chang ,  Li-Zhen Yu ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L21/823475 ,  H01L29/78696 ,  H01L29/42356

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

公开(公告)号：US20230299081A1

公开(公告)日：2023-09-21

申请号：US17695738

申请日：2022-03-15

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sairam SUBRAMANIAN ,  Walid HAFEZ ,  Charles H. WALLACE

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/66439

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition wide cut gates with extensions are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is along an end of the first gate stack in the gap. A second dielectric gate spacer is along an end of the second gate stack in the gap. A dielectric material is between and in lateral contact with the first dielectric gate spacer and the second dielectric gate spacer.