公开(公告)号：US09343401B2

公开(公告)日：2016-05-17

申请号：US14256496

申请日：2014-04-18

申请人： Siliconware Precision Industries Co., Ltd.

发明人： Chi-Liang Shih ,  Hsin-Lung Chung ,  Te-Fang Chu ,  Sheng-Ming Yang ,  Hung-Cheng Chen ,  Chia-Yang Chen

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L31/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32268 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83385 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method for fabricating a semiconductor package is provided, which includes the steps of: providing a packaging substrate having a first surface with a plurality of bonding pads and an opposite second surface; disposing a plurality of passive elements on the first surface of the packaging substrate; disposing a semiconductor chip on the passive elements through an adhesive film; electrically connecting the semiconductor chip and the bonding pads through a plurality of bonding wires; and forming an encapsulant on the first surface of the packaging substrate for encapsulating the semiconductor chip, the passive elements and the bonding wires. By disposing the passive elements between the packaging substrate and the semiconductor chip, the invention saves space on the packaging substrate and increases the wiring flexibility. Further, since the bonding wires are not easy to come into contact with the passive elements, the invention prevents a short circuit from occurring.

摘要翻译： 提供了一种制造半导体封装的方法，其包括以下步骤：提供具有多个焊盘和相对的第二表面的具有第一表面的封装基板; 在所述包装基板的第一表面上设置多个无源元件; 通过粘合膜将半导体芯片设置在无源元件上; 通过多个接合线电连接半导体芯片和接合焊盘; 以及在所述封装衬底的所述第一表面上形成密封剂以封装所述半导体芯片，所述无源元件和所述接合线。 通过在封装基板和半导体芯片之间配置无源元件，本发明节约了封装基板上的空间，增加了布线灵活性。 此外，由于接合线不容易与无源元件接触，所以本发明防止发生短路。

公开(公告)号：US20160194199A1

公开(公告)日：2016-07-07

申请号：US15067043

申请日：2016-03-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ting-Ying Chen ,  Yi Hsun Chiu ,  Ching-Hou Su ,  Chyi-Tsong Ni

IPC分类号： B81C1/00

CPC分类号： B81C1/00825 ,  B81B2207/03 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/036 ,  B81C2203/054 ,  H01L21/50 ,  H01L22/32 ,  H01L23/10 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32148 ,  H01L2224/32238 ,  H01L2224/32268 ,  H01L2224/83123 ,  H01L2224/83127 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83204 ,  H01L2224/83805 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/00 ,  H01L2224/83

摘要： A wafer seal ring may be formed on a first and/or a second wafer. One or both of the first and/or second wafers may have one or more dies formed thereon. The wafer seal ring may be formed to surround the dies of a corresponding wafer. One or more die seal rings may be formed around the one or more dies. The wafer seal ring may be formed to a height that may be approximately equal to a height of one or more die seal rings formed on the first and/or second wafer. The wafer seal ring may be formed to provide for eutectic or fusion bonding processes. The first and second wafers may be bonded together to form a seal ring structure between the first and second wafers. The seal ring structure may provide a hermetic seal between the first and second wafers.

摘要翻译： 晶片密封环可以形成在第一和/或第二晶片上。 第一和/或第二晶片中的一个或两个可以具有在其上形成的一个或多个模具。 晶片密封环可以形成为围绕相应晶片的管芯。 可以在一个或多个管芯周围形成一个或多个管芯密封环。 晶片密封环可以形成为可以大致等于形成在第一和/或第二晶片上的一个或多个模具密封环的高度的高度。 可以形成晶片密封环以提供共晶或熔接工艺。 第一和第二晶片可以结合在一起以在第一和第二晶片之间形成密封环结构。 密封环结构可以在第一和第二晶片之间提供密封。

公开(公告)号：US20140217557A1

公开(公告)日：2014-08-07

申请号：US13759549

申请日：2013-02-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ting-Ying Chen ,  Yi Hsun Chiu ,  Ching-Hou Su ,  Chyi-Tsong Ni

IPC分类号： H01L23/00

CPC分类号： B81C1/00825 ,  B81B2207/03 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/036 ,  B81C2203/054 ,  H01L21/50 ,  H01L22/32 ,  H01L23/10 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32148 ,  H01L2224/32238 ,  H01L2224/32268 ,  H01L2224/83123 ,  H01L2224/83127 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83204 ,  H01L2224/83805 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/00 ,  H01L2224/83

摘要： A wafer seal ring may be formed on a first and/or a second wafer. One or both of the first and/or second wafers may have one or more dies formed thereon. The wafer seal ring may be formed to surround the dies of a corresponding wafer. One or more die seal rings may be formed around the one or more dies. The wafer seal ring may be formed to a height that may be approximately equal to a height of one or more die seal rings formed on the first and/or second wafer. The wafer seal ring may be formed to provide for eutectic or fusion bonding processes. The first and second wafers may be bonded together to form a seal ring structure between the first and second wafers. The seal ring structure may provide a hermetic seal between the first and second wafers.

摘要翻译： 晶片密封环可以形成在第一和/或第二晶片上。 第一和/或第二晶片中的一个或两个可以具有在其上形成的一个或多个模具。 晶片密封环可以形成为围绕相应晶片的管芯。 可以在一个或多个管芯周围形成一个或多个管芯密封环。 晶片密封环可以形成为可以大致等于形成在第一和/或第二晶片上的一个或多个模具密封环的高度的高度。 可以形成晶片密封环以提供共晶或熔接工艺。 第一和第二晶片可以结合在一起以在第一和第二晶片之间形成密封环结构。 密封环结构可以在第一和第二晶片之间提供密封。

公开(公告)号：US09650243B2

公开(公告)日：2017-05-16

申请号：US15067043

申请日：2016-03-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ting-Ying Chen ,  Yi Hsun Chiu ,  Ching-Hou Su ,  Chyi-Tsong Ni

IPC分类号： H01L21/78 ,  B81C1/00 ,  H01L23/10 ,  H01L21/50 ,  H01L23/00 ,  H01L21/66

CPC分类号： B81C1/00825 ,  B81B2207/03 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/036 ,  B81C2203/054 ,  H01L21/50 ,  H01L22/32 ,  H01L23/10 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32148 ,  H01L2224/32238 ,  H01L2224/32268 ,  H01L2224/83123 ,  H01L2224/83127 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83204 ,  H01L2224/83805 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/00 ,  H01L2224/83

摘要： A wafer seal ring may be formed on a first and/or a second wafer. One or both of the first and/or second wafers may have one or more dies formed thereon. The wafer seal ring may be formed to surround the dies of a corresponding wafer. One or more die seal rings may be formed around the one or more dies. The wafer seal ring may be formed to a height that may be approximately equal to a height of one or more die seal rings formed on the first and/or second wafer. The wafer seal ring may be formed to provide for eutectic or fusion bonding processes. The first and second wafers may be bonded together to form a seal ring structure between the first and second wafers. The seal ring structure may provide a hermetic seal between the first and second wafers.

公开(公告)号：US09337182B2

公开(公告)日：2016-05-10

申请号：US13729281

申请日：2012-12-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuei-Sung Chang ,  Chun-Wen Cheng ,  Alex Kalnitsky ,  Chia-Hua Chu

IPC分类号： H01L27/06 ,  H01L25/16 ,  H01L49/02 ,  H01L23/10 ,  H01L23/00

CPC分类号： H01L27/0629 ,  H01L23/10 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/16 ,  H01L28/90 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/14051 ,  H01L2224/16268 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/32268 ,  H01L2224/73103 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/014 ,  H01L2924/00012

摘要： The present disclosure is directed to an apparatus and method for manufacture thereof. The apparatus includes a first passive substrate bonded to a second active substrate by a conductive metal interface. The conductive metal interface allows for integration of different function devices at a wafer level.

摘要翻译： 本公开涉及一种用于其制造的装置和方法。 该装置包括通过导电金属界面结合到第二有源衬底的第一无源衬底。 导电金属界面允许在晶片级集成不同功能的器件。

公开(公告)号：US20240363556A1

公开(公告)日：2024-10-31

申请号：US18139204

申请日：2023-04-25

申请人： Intel Corporation

发明人： Harald Gossner ,  Thomas Wagner ,  Bernd Waidhas ,  Georg Seidemann ,  Tae Young Yang ,  Telesphor Kamgaing

IPC分类号： H01L23/60 ,  H01L23/00 ,  H01L23/66 ,  H01Q1/50 ,  H01Q9/04

CPC分类号： H01L23/60 ,  H01L23/66 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01Q1/50 ,  H01Q9/0457 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/08147 ,  H01L2224/08267 ,  H01L2224/16267 ,  H01L2224/2929 ,  H01L2224/29499 ,  H01L2224/32267 ,  H01L2224/32268

摘要： An antenna device includes an antenna on a substrate, a low-impedance electrostatic discharge (ESD) path for an ESD pulse from the antenna to a ground terminal, and a signal path between the antenna and either a signal terminal or an integrated circuit (IC) die. The ESD and signal paths may each include separate vias through the substrate. A capacitor may couple a signal to or from the antenna and the signal terminal (or IC die) but block low-frequency power (such as an ESD pulse). The ESD path has an electrical length of a quarter of the wavelength and so may present a high impedance to ground for the signal. The antenna device may include or be coupled to an IC die. The IC die may couple to the signal and ground terminals, e.g., opposite the substrate from the antenna.

公开(公告)号：US09287188B2

公开(公告)日：2016-03-15

申请号：US13759549

申请日：2013-02-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ting-Ying Chen ,  Yi Hsun Chiu ,  Ching-Hou Su ,  Chyi-Tsong Ni

IPC分类号： H01L23/544 ,  H01L23/10 ,  H01L21/50 ,  H01L23/00 ,  B81C1/00 ,  H01L21/66

CPC分类号： B81C1/00825 ,  B81B2207/03 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/036 ,  B81C2203/054 ,  H01L21/50 ,  H01L22/32 ,  H01L23/10 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32148 ,  H01L2224/32238 ,  H01L2224/32268 ,  H01L2224/83123 ,  H01L2224/83127 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83204 ,  H01L2224/83805 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/00 ,  H01L2224/83

摘要： A wafer seal ring may be formed on a first and/or a second wafer. One or both of the first and/or second wafers may have one or more dies formed thereon. The wafer seal ring may be formed to surround the dies of a corresponding wafer. One or more die seal rings may be formed around the one or more dies. The wafer seal ring may be formed to a height that may be approximately equal to a height of one or more die seal rings formed on the first and/or second wafer. The wafer seal ring may be formed to provide for eutectic or fusion bonding processes. The first and second wafers may be bonded together to form a seal ring structure between the first and second wafers. The seal ring structure may provide a hermetic seal between the first and second wafers.

摘要翻译： 晶片密封环可以形成在第一和/或第二晶片上。 第一和/或第二晶片中的一个或两个可以具有在其上形成的一个或多个模具。 晶片密封环可以形成为围绕相应晶片的管芯。 可以在一个或多个管芯周围形成一个或多个管芯密封环。 晶片密封环可以形成为可以大致等于形成在第一和/或第二晶片上的一个或多个模具密封环的高度的高度。 可以形成晶片密封环以提供共晶或熔接工艺。 第一和第二晶片可以结合在一起以在第一和第二晶片之间形成密封环结构。 密封环结构可以在第一和第二晶片之间提供密封。

公开(公告)号：US20150245465A1

公开(公告)日：2015-08-27

申请号：US14188555

申请日：2014-02-24

申请人： Honeywell International Inc.

发明人： Lance LeRoy Sundstrom

IPC分类号： H05K1/02 ,  H05K3/30 ,  H05K1/18 ,  H01L23/367 ,  H05K1/11

CPC分类号： H05K1/0207 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/485 ,  H01L23/49822 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/16 ,  H01L2224/04026 ,  H01L2224/05571 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/29078 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/32268 ,  H01L2224/83191 ,  H01L2224/8323 ,  H01L2224/83815 ,  H01L2224/83855 ,  H01L2224/83885 ,  H01L2224/83986 ,  H01L2924/10158 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H05K1/0203 ,  H05K1/111 ,  H05K1/181 ,  H05K1/183 ,  H05K3/303 ,  H05K3/305 ,  H05K3/3442 ,  H05K2201/10446 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2924/0665 ,  H01L2924/00014

摘要： An assembly including a substrate that includes a plurality of conductive plane layers including a first group and a second group of common conductive plane layers, where electrically isolated first and second attach pads are on an edge surface of the substrate and at least thermally coupled to the first and second groups of common conductive plane layers, respectively. A surface mount technology (SMT) component, such as a thermal jumper, mounted on the first and second attach pads such that the SMT component is at least thermally coupled to the first and second groups of common conductive plane layers via the first and second attach pads, respectively. Methods of forming such an assembly also are disclosed.

摘要翻译： 一种包括衬底的组件，其包括包括第一组和第二组公共导电平面层的多个导电平面层，其中电隔离的第一和第二附接焊盘位于衬底的边缘表面上，并且至少热耦合到 第一组和第二组共同导电平面层。 安装在第一和第二附接焊盘上的表面贴装技术（SMT）部件，例如热跳线，使得SMT部件至少经由第一和第二连接热耦合到第一和第二组公共导电平面层 垫片。 公开了形成这种组件的方法。

公开(公告)号：US20240021558A1

公开(公告)日：2024-01-18

申请号：US18331150

申请日：2023-06-07

申请人： Powertech Technology Inc.

发明人： Shang-Yu CHANG-CHIEN

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16

CPC分类号： H01L24/17 ,  H01L21/561 ,  H01L21/4853 ,  H01L23/3107 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L25/165 ,  H01L24/09 ,  H01L2224/1703 ,  H01L2224/17179 ,  H01L2224/17136 ,  H01L2224/17104 ,  H01L2224/16054 ,  H01L2224/16055 ,  H01L2224/16265 ,  H01L2224/32268 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/96 ,  H01L2224/95001 ,  H01L2225/10 ,  H01L2224/09179 ,  H01L2924/384

摘要： A chip structure has a chip body having a plurality of pads, a plurality of metal bumps respectively formed on the pads, and a patterned bump directly formed on the chip body. The patterned bump has at least two different upper and lower plane patterns. A top surface of each of the metal bumps is higher than a height position on which the upper plane pattern is. When the chip structure is ground to the height position, the ground tops of the metal bumps and the upper plane pattern are flush. Therefore, detecting whether the upper plane pattern is exposed determines whether all the metal bumps are exposed and flush to each other to avoid insufficient grinding depth or over-ground.

公开(公告)号：US20150243574A1

公开(公告)日：2015-08-27

申请号：US14256496

申请日：2014-04-18

申请人： Siliconware Precision Industries Co., Ltd.

发明人： Chi-Liang Shih ,  Hsin-Lung Chung ,  Te-Fang Chu ,  Sheng-Ming Yang ,  Hung-Cheng Chen ,  Chia-Yang Chen

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

CPC分类号： H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32268 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83385 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method for fabricating a semiconductor package is provided, which includes the steps of: providing a packaging substrate having a first surface with a plurality of bonding pads and an opposite second surface; disposing a plurality of passive elements on the first surface of the packaging substrate; disposing a semiconductor chip on the passive elements through an adhesive film; electrically connecting the semiconductor chip and the bonding pads through a plurality of bonding wires; and forming an encapsulant on the first surface of the packaging substrate for encapsulating the semiconductor chip, the passive elements and the bonding wires. By disposing the passive elements between the packaging substrate and the semiconductor chip, the invention saves space on the packaging substrate and increases the wiring flexibility. Further, since the bonding wires are not easy to come into contact with the passive elements, the invention prevents a short circuit from occurring.

摘要翻译： 提供了一种制造半导体封装的方法，其包括以下步骤：提供具有多个焊盘和相对的第二表面的具有第一表面的封装基板; 在所述包装基板的第一表面上设置多个无源元件; 通过粘合膜将半导体芯片设置在无源元件上; 通过多个接合线电连接半导体芯片和接合焊盘; 以及在所述封装衬底的所述第一表面上形成密封剂以封装所述半导体芯片，所述无源元件和所述接合线。 通过在封装基板和半导体芯片之间配置无源元件，本发明节约了封装基板上的空间，增加了布线灵活性。 此外，由于接合线不容易与无源元件接触，所以本发明防止发生短路。