公开(公告)号：US12124389B2

公开(公告)日：2024-10-22

申请号：US18567253

申请日：2022-04-26

申请人： SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD

发明人： Pengshuai Li ,  Hao Fang ,  Huaixu Ma ,  Yunlong Fan

IPC分类号： G06F13/20

CPC分类号： G06F13/20

摘要： An IO task processing method includes: S1, receiving a plurality of IO tasks issued by a host and executing them separately in sequence, and making statistics of a first mean value of time consumed in processing a single IO when executed separately in sequence; S2, continuing to receive a plurality of IO tasks issued by the host, merging the IO tasks for execution, and determining an optimal IO merging time according to the first mean value of the time consumed in processing a single IO when executed separately in sequence; and S3, according to the optimal IO merging time, continuing to execute remaining IO tasks issued by the host.

公开(公告)号：US12093103B2

公开(公告)日：2024-09-17

申请号：US18058650

申请日：2022-11-23

申请人： Microchip Technology Incorporated

发明人： Eric Ching ,  Venkatraman Iyer

IPC分类号： G06F1/00 ,  G06F1/3203 ,  G06F9/4401 ,  G06F13/20 ,  G06F1/3209 ,  G06F1/3215

CPC分类号： G06F1/3203 ,  G06F9/4418 ,  G06F13/20 ,  G06F1/3209 ,  G06F1/3215

摘要： One or more examples relate, generally, to an apparatus. Such an apparatus includes a digital interface, a wake detect logic, and a power management connection. The digital interface may define a physical layer transceiver side of a connection between a physical layer transceiver and a physical layer controller, respectively of a 10SPE physical layer. The wake detect logic may communicate a source of detected wake from the physical layer transceiver to the physical layer controller via the digital interface. The power management connection may operatively couple to an enable connection of a switched voltage regulator.

公开(公告)号：US12093100B2

公开(公告)日：2024-09-17

申请号：US17033753

申请日：2020-09-26

申请人： Intel Corporation

发明人： Vivek Garg ,  Ankush Varma ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Nikethan Shivanand Baligar ,  Stephen Wang ,  Nilanjan Palit ,  Timothy Yee-Kwong Kam ,  Adwait Purandare ,  Ujjwal Gupta ,  Stanley Chen ,  Dorit Shapira ,  Shruthi Venugopal ,  Suresh Chemudupati ,  Rupal Parikh ,  Eric Dehaemer ,  Pavithra Sampath ,  Phani Kumar Kandula ,  Yogesh Bansal ,  Dean Mulla ,  Michael Tulanowski ,  Stephen Paul Haake ,  Andrew Herdrich ,  Ripan Das ,  Nazar Syed Haider ,  Aman Sewani

IPC分类号： G06F1/28 ,  G06F1/30 ,  G06F13/20

CPC分类号： G06F1/28 ,  G06F1/30 ,  G06F13/20 ,  G06F2213/40

摘要： Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US12086083B2

公开(公告)日：2024-09-10

申请号：US17892989

申请日：2022-08-22

申请人： XILINX, INC.

发明人： Jaideep Dastidar ,  David James Riddoch

IPC分类号： G06F13/20

CPC分类号： G06F13/20 ,  G06F2213/40

摘要： Embodiments herein describe creating tag bindings that can be used to assign tags to data corresponding to different tenants using a data processing unit (DPU) such as a SmartNIC, Artificial Intelligence Unit, Network Storage Unit, Database Acceleration Units, and the like. In one embodiment, the DPUs include tag gateways at the interface between a host and network element (e.g., a switch) that recognize and tag the data corresponding to the tenants. These tags are then recognized by data processing engines (DPEs) in the DPU such as AI engines, cryptographic engines, encryption engines, Direct Memory Access (DMA) engines, and the like. These DPEs can be configured to perform tag policies that provide security isolation and performance isolation between the tenants.

公开(公告)号：US20240264865A1

公开(公告)日：2024-08-08

申请号：US18641544

申请日：2024-04-22

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Thomas Anton LEYRER ,  William Cronin WALLACE ,  David Alston LIDE

IPC分类号： G06F9/48 ,  G06F1/06 ,  G06F9/448 ,  G06F9/50 ,  G06F9/52 ,  G06F11/10 ,  G06F13/20 ,  G06F13/28 ,  G06F13/40 ,  G06F16/9035 ,  H04L1/00

CPC分类号： G06F9/4881 ,  G06F1/06 ,  G06F9/448 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5038 ,  G06F9/52 ,  G06F11/1004 ,  G06F13/20 ,  G06F13/28 ,  G06F13/4068 ,  G06F16/9035 ,  H04L1/0041 ,  G06F2209/5012 ,  G06F2209/503

摘要： A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.

公开(公告)号：US12038858B2

公开(公告)日：2024-07-16

申请号：US17067334

申请日：2020-10-09

申请人： Intel Corporation

发明人： Anshuman Thakur ,  Dheeraj Subareddy ,  Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Mahesh Kumashikar ,  Sandeep Sane

IPC分类号： G06F13/20 ,  G06F13/40 ,  H01L25/16

CPC分类号： G06F13/20 ,  G06F2213/40

摘要： A processor package module comprises a substrate, one or more compute die mounted to the substrate, and one or more photonic die mounted to the substrate. The photonic die have N optical I/O links to transmit and receive optical I/O signals using a plurality of virtual optical channels, the N optical I/O links corresponding to different types of I/O interfaces excluding power and ground I/O. The substrate is mounted into a socket that support the power and ground I/O and electrical connections between the one or more compute die and the one or more photonic die.

公开(公告)号：US12028950B1

公开(公告)日：2024-07-02

申请号：US18150606

申请日：2023-01-05

申请人： Dell Products L.P.

发明人： Tyler Ryan Cox ,  Erik Summa ,  Jason Scott Morrison

IPC分类号： H05B47/105 ,  A63F13/23 ,  G06F13/20 ,  G06F16/903 ,  G06K19/07 ,  H05B47/165

CPC分类号： H05B47/105 ,  A63F13/23 ,  G06F13/20 ,  G06F16/90335 ,  G06K19/0723 ,  H05B47/165

摘要： Systems and methods described herein may provide a system that enables game play or other application sessions from a set of candidate game hosts and environments to consumption devices of a user's choice while the user moves about their home between the different environments. The system may employ methods to determine where a user is located within the home, availability and selection of candidate game hosting and target environments, homing and direction of related I/O and audio-visual (AV) content for consumption. The solution accommodates multiple users simultaneously within the home, whether in single player, multiplayer using the same screen, or multiplayer using separate screen games. The solution may configure AV and input/output (I/O) such that multiple users can consume one or multiple games in the home simultaneously, whether in separate locations or when seated together in front of the same consumption device.

公开(公告)号：US12019575B2

公开(公告)日：2024-06-25

申请号：US17404270

申请日：2021-08-17

申请人： Analog Devices, Inc.

发明人： James G. Calvin ,  Albert Rooyakkers

IPC分类号： G06F13/40 ,  G06F13/20 ,  G06F13/364 ,  G06F13/42 ,  G06F15/16 ,  G06F15/173

CPC分类号： G06F13/4022 ,  G06F13/20 ,  G06F13/364 ,  G06F13/4282 ,  G06F15/16 ,  G06F15/17312 ,  G06F2213/0004 ,  G06F2213/0022 ,  G06F2213/0024

摘要： A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

公开(公告)号：US20240202147A1

公开(公告)日：2024-06-20

申请号：US18288985

申请日：2021-12-16

申请人： Intel Corporation

发明人： Marko Bartscherer ,  Israel A. Cepeda Lopez ,  Antonio S. Cheng ,  Ke Han ,  Manjunatha Kondappa ,  Hongjun Li ,  Xinpeng Sun ,  Feng Xu ,  Xiang Ye ,  Qipeng Zha

IPC分类号： G06F13/20 ,  G06F13/42

CPC分类号： G06F13/20 ,  G06F13/4282

摘要： A system includes a processor in a lid portion of a computing device. The processor is communicatively coupled to a plurality of input/output (I/O) devices according to a plurality of I/O communication protocols via a first number of wires. The system includes a first memory coupled to the processor to store instructions that can be executed by the processor and cause the processor to receive, from a first I/O device of the plurality of I/O devices, a first message according to a first I/O communication protocol of the plurality of I/O communication protocols, convert the first message to a second message according to a host communication protocol, and send the second message over a bus containing a second number of wires traversing a hinge movably coupling the lid portion to a base portion of the computing device. The second number of wires is less than the first number of wires.

公开(公告)号：US12013800B1

公开(公告)日：2024-06-18

申请号：US18209685

申请日：2023-06-14

申请人： PROTEANTECS LTD.

发明人： Eyal Fayneh ,  Guy Redler ,  Evelyn Landman

IPC分类号： G06F13/20 ,  G01R31/317

CPC分类号： G06F13/20 ,  G01R31/31712 ,  G01R31/31725 ,  G06F2213/40

摘要： An input/output (I/O) sensor is provided for a multi-IC (Integrated Circuit) module. The I/O sensor includes: a signal input, configured to receive a data signal from an interconnected part of an IC of the multi-IC module; and a time duration measurement circuit, configured to measure a time duration between a first time, at which the data signal is at a first level, and a second time, at which the data signal is at a second level, different from the first level. The sensor may be incorporated into an I/O block, an IC, and/or a multi-IC module.