公开(公告)号：US20240202147A1

公开(公告)日：2024-06-20

申请号：US18288985

申请日：2021-12-16

申请人： Intel Corporation

发明人： Marko Bartscherer ,  Israel A. Cepeda Lopez ,  Antonio S. Cheng ,  Ke Han ,  Manjunatha Kondappa ,  Hongjun Li ,  Xinpeng Sun ,  Feng Xu ,  Xiang Ye ,  Qipeng Zha

IPC分类号： G06F13/20 ,  G06F13/42

CPC分类号： G06F13/20 ,  G06F13/4282

摘要： A system includes a processor in a lid portion of a computing device. The processor is communicatively coupled to a plurality of input/output (I/O) devices according to a plurality of I/O communication protocols via a first number of wires. The system includes a first memory coupled to the processor to store instructions that can be executed by the processor and cause the processor to receive, from a first I/O device of the plurality of I/O devices, a first message according to a first I/O communication protocol of the plurality of I/O communication protocols, convert the first message to a second message according to a host communication protocol, and send the second message over a bus containing a second number of wires traversing a hinge movably coupling the lid portion to a base portion of the computing device. The second number of wires is less than the first number of wires.