公开(公告)号：US20220100247A1

公开(公告)日：2022-03-31

申请号：US17033753

申请日：2020-09-26

申请人： Intel Corporation

发明人： Vivek Garg ,  Ankush Varma ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Nikethan Shivanand Baligar ,  Stephen Wang ,  Nilanjan Palit ,  Timothy Kam ,  Adwait Purandare ,  Ujjwal Gupta ,  Stanley Chen ,  Dorit Shapira ,  Shruthi Venugopal ,  Suresh Chemudupati ,  Rupal Parikh ,  Eric Dehaemer ,  Pavithra Sampath ,  Phani Kumar Kandula ,  Yogesh Bansal ,  Dean Mulla ,  Michael Tulanowski ,  Stephen Haake ,  Andrew Herdrich ,  Ripan Das

IPC分类号： G06F1/28 ,  G06F1/30 ,  G06F13/20

摘要： Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US10579125B2

公开(公告)日：2020-03-03

申请号：US15055578

申请日：2016-02-27

申请人： Intel Corporation

发明人： Daniel J. Ragland ,  Pavithra Sampath ,  Kirk Pfaender ,  Kahraman D. Akdemir ,  Ariel Gur

IPC分类号： G06F1/324 ,  G06F9/30

摘要： An integrated circuit of an aspect includes a power control unit having an interface to receive an indication that one or more instructions of a first type are to be performed by a core. The power control unit also has logic to control a maximum clock frequency for the core based on the indication that the instructions of the first type are to be performed by the core.

公开(公告)号：US12093100B2

公开(公告)日：2024-09-17

申请号：US17033753

申请日：2020-09-26

申请人： Intel Corporation

发明人： Vivek Garg ,  Ankush Varma ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Nikethan Shivanand Baligar ,  Stephen Wang ,  Nilanjan Palit ,  Timothy Yee-Kwong Kam ,  Adwait Purandare ,  Ujjwal Gupta ,  Stanley Chen ,  Dorit Shapira ,  Shruthi Venugopal ,  Suresh Chemudupati ,  Rupal Parikh ,  Eric Dehaemer ,  Pavithra Sampath ,  Phani Kumar Kandula ,  Yogesh Bansal ,  Dean Mulla ,  Michael Tulanowski ,  Stephen Paul Haake ,  Andrew Herdrich ,  Ripan Das ,  Nazar Syed Haider ,  Aman Sewani

IPC分类号： G06F1/28 ,  G06F1/30 ,  G06F13/20

CPC分类号： G06F1/28 ,  G06F1/30 ,  G06F13/20 ,  G06F2213/40

摘要： Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US09874910B2

公开(公告)日：2018-01-23

申请号：US14471572

申请日：2014-08-28

申请人： Intel Corporation

发明人： Tessil Thomas ,  Phani Kumar Kandula ,  Jayakrishna Guddeti ,  Chandra P. Joshi ,  Junaid F. Thaliyil ,  Pavithra Sampath

IPC分类号： G06F1/24 ,  G06F13/42

CPC分类号： G06F1/24 ,  G06F13/4221 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/14 ,  Y02D10/151

摘要： In an embodiment, a processor includes at least one core to initiate a hot reset, and a peripheral device that is coupled to a root complex fabric via through the root port via an peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge. The processor also includes a power control unit that includes reset logic to decouple the peripheral device from the root complex fabric responsive to initiation of the hot reset. After the peripheral device is decoupled from the root complex fabric, the reset logic is to assert a reset of the peripheral device while a first core of the at least one core is in operation. Other embodiments are described and claimed.

公开(公告)号：US20160062424A1

公开(公告)日：2016-03-03

申请号：US14471572

申请日：2014-08-28

申请人： Intel Corporation

发明人： Tessil Thomas ,  Phani Kumar Kandula ,  Jayakrishna Guddeti ,  Chandra P. Joshi ,  Junaid F. Thaliyil ,  Pavithra Sampath

IPC分类号： G06F1/24 ,  G06F9/44 ,  G06F13/42

CPC分类号： G06F1/24 ,  G06F13/4221 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/14 ,  Y02D10/151

摘要： In an embodiment, a processor includes at least one core to initiate a hot reset, and a peripheral device that is coupled to a root complex fabric via through the root port via an peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge. The processor also includes a power control unit that includes reset logic to decouple the peripheral device from the root complex fabric responsive to initiation of the hot reset. After the peripheral device is decoupled from the root complex fabric, the reset logic is to assert a reset of the peripheral device while a first core of the at least one core is in operation. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括至少一个核心来启动热复位，以及外围设备，其经由外部组件互连通过根端口与根组合架构耦合到片上系统架构（PCIE至OSF ）桥。 处理器还包括功率控制单元，其包括复位逻辑，以响应于热复位的启动来将外围设备与根复杂结构分离。 在外围设备与根复杂结构解耦之后，复位逻辑是在至少一个核心的第一核心正在运行时断言外围设备的复位。 描述和要求保护其他实施例。