In an embodiment, a processor includes at least one core to initiate a hot reset, and a peripheral device that is coupled to a root complex fabric via through the root port via an peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge. The processor also includes a power control unit that includes reset logic to decouple the peripheral device from the root complex fabric responsive to initiation of the hot reset. After the peripheral device is decoupled from the root complex fabric, the reset logic is to assert a reset of the peripheral device while a first core of the at least one core is in operation. Other embodiments are described and claimed.