公开(公告)号：US20210318742A1

公开(公告)日：2021-10-14

申请号：US17354821

申请日：2021-06-22

申请人： Intel Corporation

发明人： Dorit Shapira ,  Anand Enamandram ,  Daniel Cartagena ,  Krishnakanth Sistla ,  Jorge P. Rodriguez ,  Efraim Rotem ,  Nir Rosenzweig

IPC分类号： G06F1/3206 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/3234

摘要： An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.

公开(公告)号：US08700933B2

公开(公告)日：2014-04-15

申请号：US13787085

申请日：2013-03-06

申请人： Intel Corporation

发明人： Yen-Cheng Liu ,  P Keong Or ,  Krishnakanth Sistla ,  Ganapati Srinivasa

IPC分类号： G06F1/26 ,  G06F1/22

CPC分类号： G06F1/3243 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0811 ,  G06F15/80 ,  G06F2212/283 ,  G11C7/1072 ,  G11C7/1075 ,  Y02D10/16

摘要： A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

摘要翻译： 公开了一种监视架构事件的方法和装置。 架构事件通过推送总线机制链接在一起，每个架构事件都具有指定的时隙。 在每个核心中至少有一个分支的推送总线。 推送总线的每个分支可以监视一个核心与所有的架构事件。 然后将通过推送总线从事件收集的所有数据发送到电源控制单元。

公开(公告)号：US12093100B2

公开(公告)日：2024-09-17

申请号：US17033753

申请日：2020-09-26

申请人： Intel Corporation

发明人： Vivek Garg ,  Ankush Varma ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Nikethan Shivanand Baligar ,  Stephen Wang ,  Nilanjan Palit ,  Timothy Yee-Kwong Kam ,  Adwait Purandare ,  Ujjwal Gupta ,  Stanley Chen ,  Dorit Shapira ,  Shruthi Venugopal ,  Suresh Chemudupati ,  Rupal Parikh ,  Eric Dehaemer ,  Pavithra Sampath ,  Phani Kumar Kandula ,  Yogesh Bansal ,  Dean Mulla ,  Michael Tulanowski ,  Stephen Paul Haake ,  Andrew Herdrich ,  Ripan Das ,  Nazar Syed Haider ,  Aman Sewani

IPC分类号： G06F1/28 ,  G06F1/30 ,  G06F13/20

CPC分类号： G06F1/28 ,  G06F1/30 ,  G06F13/20 ,  G06F2213/40

摘要： Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US20190155729A1

公开(公告)日：2019-05-23

申请号：US16044092

申请日：2018-07-24

申请人： Intel Corporation

发明人： Krishnakanth Sistla ,  Yen-Cheng Liu ,  Zhong-Ning Cai

IPC分类号： G06F12/084 ,  G06F12/0811 ,  G06F12/0831

摘要： A method and apparatus for improving snooping performance is disclosed. In one embodiment, one or more content addressable matches are used to determine where and when an address conflict occurs. Depending upon the timing, a read request or a snoop request may be set for retry. In another embodiment, an age order matrix may be used to determine when several core snoop requests may be issued during a same time period, so that the snoops may be processed during this time period.

公开(公告)号：US09075614B2

公开(公告)日：2015-07-07

申请号：US13782492

申请日：2013-03-01

申请人： Intel Corporation

发明人： Eric Fetzer ,  Reid Riedlinger ,  Don Soltis ,  William Bowhill ,  Satish Shrimali ,  Krishnakanth Sistla ,  Efraim Rotem ,  Rakesh Kumar ,  Vivek Garg ,  Alon Naveh ,  Lokesh Sharma

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3296 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.

摘要翻译： 处理器可以包括核心和无孔区域。 可以通过控制处理器的Cdyn来控制核心区域消耗的功率，使得Cdyn处于可允许的Cdyn值内，而不管应用程序是否被核心区域处理。 电源管理技术包括测量数字活动因素（DAF），监控架构和数据活动级别，以及通过基于活动级别来限制指令来控制功耗。 作为节流指令的结果，节流可以在第3垂直和热设计点（TDP）中实现。 此外，通过改变提供给无孔区域的参考电压VR和VP，可以减少核心区域处于深功率节省状态时由无孔区域消耗的空闲功率。 结果，可以减少由无孔区域消耗的空闲功率。

公开(公告)号：US11301298B2

公开(公告)日：2022-04-12

申请号：US16833595

申请日：2020-03-28

申请人： Intel Corporation

发明人： Ankush Varma ,  Nikhil Gupta ,  Vasudevan Srinivasan ,  Krishnakanth Sistla ,  Nilanjan Palit ,  Abhinav Karhu ,  Eugene Gorbatov ,  Eliezer Weissmann

IPC分类号： G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

摘要： An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores; wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core, wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.

公开(公告)号：US11054877B2

公开(公告)日：2021-07-06

申请号：US16012623

申请日：2018-06-19

申请人： Intel Corporation

发明人： Dorit Shapira ,  Anand K. Enamandram ,  Daniel Cartagena ,  Krishnakanth Sistla ,  Jorge P. Rodriguez ,  Efraim Rotem ,  Nir Rosenzweig

IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/3234 ,  H03M1/12

摘要： An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.

公开(公告)号：US10429912B2

公开(公告)日：2019-10-01

申请号：US15846161

申请日：2017-12-18

申请人： Intel Corporation

发明人： Krishnakanth Sistla ,  Martin Rowland ,  Efraim Rotem ,  Brian J. Griffith ,  Ankush Varma ,  Anupama Suryanarayanan

IPC分类号： G06F1/26 ,  G06F1/329 ,  G06F1/3203 ,  G06F1/3234

摘要： A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.

公开(公告)号：US20180373287A1

公开(公告)日：2018-12-27

申请号：US15632000

申请日：2017-06-23

申请人： Intel Corporation

发明人： Asma H. Al-Rawi ,  Federico Ardanaz ,  Jonathan M. Eastep ,  Dorit Shapira ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Vasudevan Srinivasan ,  Chris MacNamara

IPC分类号： G06F1/06 ,  G06F1/04 ,  G06F1/08 ,  G06F9/50

摘要： An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.

公开(公告)号：US09268393B2

公开(公告)日：2016-02-23

申请号：US13997295

申请日：2012-11-30

申请人： Intel Corporation

发明人： Ankush Varma ,  Krishnakanth Sistla ,  Martin T. Rowland ,  Brian J. Griffith ,  Viktor D. Vogman ,  Joseph R. Doucette ,  Eric J. Dehaemer ,  Vivek Garg ,  Chris Poirier ,  Jeremy J. Shrall ,  Avinash N. Ananthakrishnan ,  Stephen H. Gunther

IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F1/06 ,  G06F9/45

CPC分类号： G06F1/3234 ,  G06F1/06 ,  G06F1/324 ,  G06F8/4432 ,  Y02D10/126

摘要： In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令，多个图形引擎各自独立地执行图形操作; 以及功率控制单元，其耦合到所述多个核以控制所述处理器的功率消耗，其中所述功率控制单元包括功率偏移控制逻辑，以将所述处理器的功率消耗水平限制在高于限定功率极限以上 工作周期的占空比部分。 描述和要求保护其他实施例。