公开(公告)号：US20230195918A1

公开(公告)日：2023-06-22

申请号：US17645070

申请日：2021-12-20

申请人： Intel Corporation

发明人： Stanley Chen ,  Vivek Garg ,  Ankush Varma ,  Eric J. Dehaemer ,  Johan van de Groenendaal

IPC分类号： G06F21/62 ,  G06F9/30

CPC分类号： G06F21/6218 ,  G06F9/30101

摘要： In an embodiment, a processor may include at least one processing engine to execute instructions, and a register interface circuit coupled to the at least one processing engine. The register interface circuit may be to: receive a request to access a register associated with a feature of the processor; determine whether the requested access is authorized based at least in part on an entry of an access structure, the access structure to store a plurality of entries associated with a plurality of features of the processor; and in response to a determination that the requested access is authorized by the access structure, perform the requested access of the register associated with the feature. Other embodiments are described and claimed.

公开(公告)号：US11308680B2

公开(公告)日：2022-04-19

申请号：US17158842

申请日：2021-01-26

申请人： Intel Corporation

发明人： Ankur Shah ,  Matthew Callaway ,  Vivek Garg ,  Rajeev K Nalawadi ,  James Varga

IPC分类号： G06T1/20 ,  G06T15/00 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F1/28

摘要： Apparatus and method for processing virtual graphics processor telemetry data based on quanta. For example, one embodiment of a graphics processing apparatus comprises virtualization control circuitry to virtualize graphics processing resources of one or more graphics processing units (GPU), wherein one or more virtual machines (VMs) are to be provided with controlled access to the graphics processing resources in accordance with a current graphics virtualization configuration specified, at least in part, in one or more virtualization control registers of the virtualization control circuitry; a scheduler to schedule each VM for processing by the graphics processing resources in accordance with the graphics virtualization configuration, the scheduler to generate a VM switch event responsive to each VM being scheduled for processing on the graphics processing resources; power management circuitry to collect telemetry data associated with VMs which have temporarily completed processing on the graphics processing resources and to forward the telemetry data to a telemetry data aggregator, the telemetry data aggregator to combine telemetry data collected for each VM over a period of time and to store per-VM telemetry data in a data repository accessible by a virtualization management application.

公开(公告)号：US11169560B2

公开(公告)日：2021-11-09

申请号：US16480830

申请日：2017-02-24

申请人： INTEL CORPORATION

发明人： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris Macnamara ,  John J. Browne ,  Ripan Das

IPC分类号： G06G1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324 ,  G06F1/08

摘要： A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US09760409B2

公开(公告)日：2017-09-12

申请号：US15162709

申请日：2016-05-24

申请人： Intel Corporation

发明人： Krishnakanth V. Sistla ,  Mark Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Daniel Borkowski ,  Vivek Garg ,  Chelsea Akturan ,  Avinash N. Ananthakrishnan

IPC分类号： G06F1/32 ,  G06F9/50

CPC分类号： G06F9/5094 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/171

摘要： In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.

公开(公告)号：US09760155B2

公开(公告)日：2017-09-12

申请号：US14960693

申请日：2015-12-07

申请人： Intel Corporation

发明人： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC分类号： G06F1/32 ,  G06F1/00 ,  G06F1/26

CPC分类号： G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

公开(公告)号：US20170177046A1

公开(公告)日：2017-06-22

申请号：US14970747

申请日：2015-12-16

申请人： Intel Corporation

发明人： Vivek Garg ,  Alexander Gendler ,  Arvind Raman ,  Ashish V. Choubal ,  Krishnakanth V. Sistla ,  Dean Mulla ,  Eric J. Dehaemer ,  Rahul Agrawal ,  Guy G. Sotomayor

IPC分类号： G06F1/26

CPC分类号： G06F1/26 ,  G06F1/3243 ,  Y02D10/152

摘要： In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.

公开(公告)号：US09405351B2

公开(公告)日：2016-08-02

申请号：US13716712

申请日：2012-12-17

申请人： Intel Corporation

发明人： Ankush Varma ,  Krishnakanth V. Sistla ,  Ian M. Steiner ,  Vivek Garg ,  Chris Poirier ,  Martin T. Rowland

IPC分类号： G06F1/26 ,  G06F1/32 ,  G06T1/20 ,  G06F13/00 ,  G06F9/50 ,  G06F15/173

CPC分类号： G06F1/324 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/5044 ,  G06F9/505 ,  G06F13/00 ,  G06F15/17325 ,  G06T1/20 ,  Y02D10/126

摘要： In an embodiment, a processor includes a core to execute instructions, uncore logic coupled to the core, and a power controller to control a power consumption level. The power controller is configured to determine an activity level of the processor and responsive to this level, to generate a request for communication to a second processor coupled to the processor to request frequency coordination between the processors. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括执行指令的核心，耦合到核心的非逻辑逻辑以及用于控制功耗水平的功率控制器。 功率控制器被配置为确定处理器的活动级别并响应于该级别，以产生与耦合到处理器的第二处理器通信以请求处理器之间的频率协调的请求。 描述和要求保护其他实施例。

公开(公告)号：US12093100B2

公开(公告)日：2024-09-17

申请号：US17033753

申请日：2020-09-26

申请人： Intel Corporation

发明人： Vivek Garg ,  Ankush Varma ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Nikethan Shivanand Baligar ,  Stephen Wang ,  Nilanjan Palit ,  Timothy Yee-Kwong Kam ,  Adwait Purandare ,  Ujjwal Gupta ,  Stanley Chen ,  Dorit Shapira ,  Shruthi Venugopal ,  Suresh Chemudupati ,  Rupal Parikh ,  Eric Dehaemer ,  Pavithra Sampath ,  Phani Kumar Kandula ,  Yogesh Bansal ,  Dean Mulla ,  Michael Tulanowski ,  Stephen Paul Haake ,  Andrew Herdrich ,  Ripan Das ,  Nazar Syed Haider ,  Aman Sewani

IPC分类号： G06F1/28 ,  G06F1/30 ,  G06F13/20

CPC分类号： G06F1/28 ,  G06F1/30 ,  G06F13/20 ,  G06F2213/40

摘要： Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US11703906B2

公开(公告)日：2023-07-18

申请号：US17520296

申请日：2021-11-05

申请人： Intel Corporation

发明人： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC分类号： G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324

CPC分类号： G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/30101 ,  G06F9/45558 ,  G06F2009/45591

摘要： A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US10545793B2

公开(公告)日：2020-01-28

申请号：US15720296

申请日：2017-09-29

申请人： Intel Corporation

发明人： Avinash N. Ananthakrishnan ,  Vijay Dhanraj ,  Russell J. Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen H. Gunther ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F9/30

摘要： In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.