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公开(公告)号：US11169560B2
公开(公告)日：2021-11-09
申请号：US16480830
申请日：2017-02-24
Applicant: INTEL CORPORATION
Inventor： Vasudevan Srinivasan , Krishnakanth V. Sistla , Corey D. Gough , Ian M. Steiner , Nikhil Gupta , Vivek Garg , Ankush Varma , Sujal A. Vora , David P. Lerner , Joseph M. Sullivan , Nagasubramanian Gurumoorthy , William J. Bowhill , Venkatesh Ramamurthy , Chris Macnamara , John J. Browne , Ripan Das
Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
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公开(公告)号：US10956345B2
公开(公告)日：2021-03-23
申请号：US15088429
申请日：2016-04-01
Applicant: Intel Corporation
Inventor： Gaurav Khanna , Prashant Sethi , Venkatesh Ramamurthy
IPC: G06F13/24 , G06F1/3206 , G06F9/4401
Abstract: A method is described. The method includes determining that a first of a plurality of processor cores in a multi-processor computing system has entered an idle state, triggering a SMI for the first processor core, the first processor core entering a system management mode (SMM) and performing one or more platform management operations.
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公开(公告)号：US20170185128A1
公开(公告)日：2017-06-29
申请号：US14757561
申请日：2015-12-24
Applicant: INTEL CORPORATION
Inventor： Venkatesh Ramamurthy , Ripan Das
IPC: G06F1/32
CPC classification number: G06F1/3203 , G06F1/10 , G06F1/3237 , G06F1/3287 , Y02D10/171
Abstract: An electronic device may be provided that includes logic, at least a portion which is hardware, to receive a plurality of transition requests within a configurable moving time period and to block a clock signal to one or more of the plurality of cores based on the received transition requests.
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公开(公告)号：US12066853B2
公开(公告)日：2024-08-20
申请号：US18329492
申请日：2023-06-05
Applicant: Intel Corporation
Inventor： Vasudevan Srinivasan , Krishnakanth V. Sistla , Corey D. Gough , Ian M. Steiner , Nikhil Gupta , Vivek Garg , Ankush Varma , Sujal A. Vora , David P. Lerner , Joseph M. Sullivan , Nagasubramanian Gurumoorthy , William J. Bowhill , Venkatesh Ramamurthy , Chris MacNamara , John J. Browne , Ripan Das
IPC: G06F1/08 , G06F1/3203 , G06F1/324 , G06F9/30 , G06F9/455
CPC classification number: G06F1/08 , G06F1/3203 , G06F1/324 , G06F9/30101 , G06F9/45558 , G06F2009/45591 , Y02D10/00
Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
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公开(公告)号：US20230315143A1
公开(公告)日：2023-10-05
申请号：US18329492
申请日：2023-06-05
Applicant: Intel Corporation
Inventor： Vasudevan Srinivasan , Krishnakanth V. Sistla , Corey D. Gough , Ian M. Steiner , Nikhil Gupta , Vivek Garg , Ankush Varma , Sujal A. Vora , David P. Lerner , Joseph M. Sullivan , Nagasubramanian Gurumoorthy , William J. Bowhill , Venkatesh Ramamurthy , Chris MacNamara , John J. Browne , Ripan Das
IPC: G06F1/08 , G06F1/3203 , G06F9/30 , G06F9/455 , G06F1/324
CPC classification number: G06F1/08 , G06F1/3203 , G06F9/30101 , G06F9/45558 , G06F1/324 , G06F2009/45591
Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
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Patent Agency Ranking
公开(公告)号：US10373124B2
公开(公告)日：2019-08-06
申请号：US15371115
申请日：2016-12-06
Applicant: Intel Corporation
Inventor： Gyan Prakash , Nagasubramanian Gurumoorthy , Saurabh Dadu , Venkatesh Ramamurthy , Rama Sawhney
Abstract: Technologies for generating tasks from communication messages includes a mobile computing device for monitoring communication messages, parsing the communication messages to detect content indicative of upcoming tasks, generating a task for each of the upcoming tasks detected, generating a task list from the generated tasks, and generating an alarm for each task. Additionally, the mobile computing device receives tasks generated by a cloud server.
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公开(公告)号：US20180107490A1
公开(公告)日：2018-04-19
申请号：US15695499
申请日：2017-09-05
Applicant: Intel Corporation
Inventor： Rajesh Poornachandran , Vincent J. Zimmer , Karunakara Kotary , Venkatesh Ramamurthy , Pralhad M. Madhavi
IPC: G06F9/4401 , G06F1/32
CPC classification number: G06F9/4401 , G06F1/3203 , G06F1/3212 , G06F1/3287 , Y02D10/171 , Y02D10/174 , Y02D50/20
Abstract: Technologies for fast low-power startup include a computing device with a processor having a power management integrated circuit. The computing device initializes platform components into a low-power state and determines, in a pre-boot firmware environment, the battery state of the computing device. The computing device determines a minimum-power startup (MPS) configuration that identifies platform components to be energized and determines whether the battery state is sufficient for the MPS configuration. If sufficient, the computing device energizes the platform components of the MPS configuration and boots into an MPS boot mode. In the MPS boot mode, the computing device may execute one or more user-configured application(s). If the battery state is sufficient for normal operation, the computing device may boot into a normal mode. In the normal mode, the user may configure the MPS configuration by selecting features for the future MPS boot mode. Other embodiments are described and claimed.
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公开(公告)号：US09378352B2
公开(公告)日：2016-06-28
申请号：US13763116
申请日：2013-02-08
Applicant: Intel Corporation
Inventor： Gyan Prakash , Venkatesh Ramamurthy , Hong Li , Jesse Walker
CPC classification number: G06F21/35 , G06F21/36 , H04L63/0853 , H04L2463/082 , H04W12/06
Abstract: Mobile device, client device and server associated with client-server authentication are described. In embodiments, the mobile device may comprise a camera and a token extractor. The token extractor may be coupled to the camera and configured to analyze an image, captured by the camera. The captured image may contain a barcode and may be displayed on a client device in response to a request of a server for access to a resource. The barcode may contain a token, which may be extracted by the token extractor to be used to gain access to a resource requested from a server. Other embodiments may be described and/or claimed.
Abstract translation: 描述了与客户机 - 服务器认证相关联的移动设备，客户端设备和服务器。 在实施例中，移动设备可以包括相机和令牌提取器。 令牌提取器可以耦合到相机并且被配置为分析由相机捕获的图像。 捕获的图像可以包含条形码，并且可以响应于服务器访问资源的请求而在客户端设备上显示。 条形码可以包含令牌，其可以由令牌提取器提取以被用于获得对从服务器请求的资源的访问。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US11703906B2
公开(公告)日：2023-07-18
申请号：US17520296
申请日：2021-11-05
Applicant: Intel Corporation
Inventor： Vasudevan Srinivasan , Krishnakanth V. Sistla , Corey D. Gough , Ian M. Steiner , Nikhil Gupta , Vivek Garg , Ankush Varma , Sujal A. Vora , David P. Lerner , Joseph M. Sullivan , Nagasubramanian Gurumoorthy , William J. Bowhill , Venkatesh Ramamurthy , Chris MacNamara , John J. Browne , Ripan Das
IPC: G06F1/08 , G06F1/3203 , G06F9/30 , G06F9/455 , G06F1/324
CPC classification number: G06F1/08 , G06F1/3203 , G06F1/324 , G06F9/30101 , G06F9/45558 , G06F2009/45591
Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
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公开(公告)号：US20170083876A1
公开(公告)日：2017-03-23
申请号：US15371115
申请日：2016-12-06
Applicant: Intel Corporation
Inventor： Gyan Prakash , Nagasubramanian Gurumoorthly , Saurabh Dadu , Venkatesh Ramamurthy , Rama Sawhney
CPC classification number: G06Q10/1097 , G01C21/00 , G06F3/01 , G06Q10/109 , G06Q99/00 , H04L51/12 , H04L51/16 , H04L67/22 , H04W4/029
Abstract: Technologies for generating tasks from communication messages includes a mobile computing device for monitoring communication messages, parsing the communication messages to detect content indicative of upcoming tasks, generating a task for each of the upcoming tasks detected, generating a task list from the generated tasks, and generating an alarm for each task. Additionally, the mobile computing device receives tasks generated by a cloud server.
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