公开(公告)号：US09910470B2

公开(公告)日：2018-03-06

申请号：US14970747

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Alexander Gendler ,  Arvind Raman ,  Ashish V. Choubal ,  Krishnakanth V. Sistla ,  Dean Mulla ,  Eric J. Dehaemer ,  Rahul Agrawal ,  Guy G. Sotomayor

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/3243 ,  Y02D10/152

Abstract: In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.

公开(公告)号：US20220206945A1

公开(公告)日：2022-06-30

申请号：US17134254

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Carl J. Beckmann ,  Samantika S. Sury ,  Christopher J. Hughes ,  Lingxiang Xiang ,  Rahul Agrawal

IPC: G06F12/0811 ,  G06F12/0817 ,  G06F12/0862 ,  G06F12/084

Abstract: Disclosed embodiments relate to atomic memory operations. In one example, an apparatus includes multiple processor cores, a cache hierarchy, a local execution unit, and a remote execution unit, and an adaptive remote atomic operation unit. The cache hierarchy includes a local cache at a first level and a shared cache at a second level. The local execution unit is to perform an atomic operation at the first level if the local cache is a storing a cache line including data for the atomic operation. The remote execution unit is to perform the atomic operation at the second level. The adaptive remote atomic operation unit is to determine whether to perform the first atomic operation at the first level or at the second level and whether to copy the cache line from the shared cache to the local cache.

公开(公告)号：US12216579B2

公开(公告)日：2025-02-04

申请号：US17134254

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Carl J. Beckmann ,  Samantika S. Sury ,  Christopher J. Hughes ,  Lingxiang Xiang ,  Rahul Agrawal

IPC: G06F12/0811 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/0862

Abstract: Disclosed embodiments relate to atomic memory operations. In one example, an apparatus includes multiple processor cores, a cache hierarchy, a local execution unit, and a remote execution unit, and an adaptive remote atomic operation unit. The cache hierarchy includes a local cache at a first level and a shared cache at a second level. The local execution unit is to perform an atomic operation at the first level if the local cache is a storing a cache line including data for the atomic operation. The remote execution unit is to perform the atomic operation at the second level. The adaptive remote atomic operation unit is to determine whether to perform the first atomic operation at the first level or at the second level and whether to copy the cache line from the shared cache to the local cache.

公开(公告)号：US20170177046A1

公开(公告)日：2017-06-22

申请号：US14970747

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Alexander Gendler ,  Arvind Raman ,  Ashish V. Choubal ,  Krishnakanth V. Sistla ,  Dean Mulla ,  Eric J. Dehaemer ,  Rahul Agrawal ,  Guy G. Sotomayor

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3243 ,  Y02D10/152

Abstract: In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.