Generation of processor interrupts using averaged data

    公开(公告)号:US11016916B2

    公开(公告)日:2021-05-25

    申请号:US16868603

    申请日:2020-05-07

    申请人: Intel Corporation

    摘要: In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.

    Generation of processor interrupts using averaged data

    公开(公告)号:US10657083B2

    公开(公告)日:2020-05-19

    申请号:US15281472

    申请日:2016-09-30

    申请人: Intel Corporation

    摘要: In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.

    Multi-level loops for computer processor control

    公开(公告)号:US10216246B2

    公开(公告)日:2019-02-26

    申请号:US15281651

    申请日:2016-09-30

    申请人: Intel Corporation

    摘要: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

    Apparatus and method for controlling the reliability stress rate on a processor
    7.
    发明授权
    Apparatus and method for controlling the reliability stress rate on a processor 有权
    用于控制处理器上的可靠性应力率的装置和方法

    公开(公告)号:US09317389B2

    公开(公告)日:2016-04-19

    申请号:US13931115

    申请日:2013-06-28

    申请人: INTEL CORPORATION

    IPC分类号: G06F11/00 G06F11/30

    摘要: An apparatus and method for tracking stress on a processor and responsively controlling operating conditions. For example, one embodiment of a processor comprises: stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; and stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate.

    摘要翻译: 用于跟踪处理器上的应力并响应于控制操作条件的装置和方法。 例如,处理器的一个实施例包括:应力跟踪逻辑,用于基于处理器的一个或多个部分的当前操作条件来确定处理器的一个或多个部分所经受的应力; 以及压力控制逻辑,以基于所确定的应力和目标应力累积速率来控制处理器的一个或多个操作特性。

    Providing Lifetime Statistical Information For A Processor
    8.
    发明申请
    Providing Lifetime Statistical Information For A Processor 有权
    为处理器提供终身统计信息

    公开(公告)号:US20160070321A1

    公开(公告)日:2016-03-10

    申请号:US14482148

    申请日:2014-09-10

    申请人: Intel Corporation

    IPC分类号: G06F1/26 G06F1/32

    摘要: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,处理器包括多个核和耦合到核的功率控制单元(PCU)。 PCU具有应力检测器,用于接收处理器运行的电压和温度,并计算包括有效可靠性压力在内的寿命统计信息,在诸如个人计算机,服务器计算机等计算系统的多个引导周期之后维持寿命统计信息, 平板电脑,智能电话或任何其他计算平台,基于生存期统计信息来控制处理器的一个或多个操作参数,并且经由接口将至少一部分生命周期统计信息传达给用户和/或管理实体 的处理器。 描述和要求保护其他实施例。

    BALANCED CONTROL OF PROCESSOR TEMPERATURE
    9.
    发明申请
    BALANCED CONTROL OF PROCESSOR TEMPERATURE 有权
    加工温度平衡控制

    公开(公告)号:US20160048181A1

    公开(公告)日:2016-02-18

    申请号:US14461039

    申请日:2014-08-15

    申请人: Intel Corporation

    IPC分类号: G06F1/20 G06F1/32 G01K13/00

    摘要: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,处理器包括多个核心和多个温度传感器,其中每个核心靠近至少一个温度传感器。 该处理器还包括一个功率控制单元(PCU),其包括用于接收包括来自每个温度传感器的相应温度值的温度数据的温度逻辑。 响应于温度数据的最高温度值超过阈值的指示,温度逻辑是根据基于多个核心中的至少两个的指令执行特性的确定的策略来调整多个域频率。 每个域频率与包括多个核心中的至少一个核心的对应域相关联,并且每个域频率是可独立调整的。 描述和要求保护其他实施例。