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公开(公告)号：US20220103185A1
公开(公告)日：2022-03-31
申请号：US17490946
申请日：2021-09-30
申请人： Intel Corporation
发明人： Patrick Connor , Kapil Sood , Scott Dubal , Andrew Herdrich , James Hearn
摘要： Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.
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公开(公告)号：US20190103881A1
公开(公告)日：2019-04-04
申请号：US15720400
申请日：2017-09-29
申请人： Intel Corporation
发明人： Patrick Connor , Kapil Sood , Scott Dubal , Andrew Herdrich , James Hearn
摘要： Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.
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公开(公告)号：US20170351534A1
公开(公告)日：2017-12-07
申请号：US15629882
申请日：2017-06-22
申请人： Intel Corporation
IPC分类号： G06F9/445 , G06F1/10 , G06F9/50 , G06F1/32 , G06F12/0891
CPC分类号： G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
摘要： An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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公开(公告)号：US20230315632A1
公开(公告)日：2023-10-05
申请号：US17711471
申请日：2022-04-01
申请人： Intel Corporation
发明人： Philip Abraham , Stephen Van Doren , Ritu Gupta , Andrew Herdrich
IPC分类号： G06F12/0811 , G06F12/0846 , G06F12/084
CPC分类号： G06F12/0811 , G06F12/0846 , G06F12/084
摘要： Techniques and mechanisms to facilitate access to a cache based on a dual basis partition scheme. In an embodiment, a first one or more registers of a processor provide information which describes multiple set-wise partitions of a cache. A second one or more registers of the processor provides additional information which describes multiple way-wise partitions of the cache. A virtual cache is defined as that region of the cache which is both in a particular set-wise partition, and in a particular way-wise partition. In another embodiment, a cache agent of the processor performs operations, based on the set-wise partitioning and the way-wise partitioning, to determine a mapping of one address—which is provided in a memory access request, and which indicates a location in one virtual cache—to another address which indicates another location in a different virtual cache.
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公开(公告)号：US11515890B2
公开(公告)日：2022-11-29
申请号：US17490946
申请日：2021-09-30
申请人： Intel Corporation
发明人： Patrick Connor , Kapil Sood , Scott Dubal , Andrew Herdrich , James Hearn
摘要： Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.
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公开(公告)号：US20220100247A1
公开(公告)日：2022-03-31
申请号：US17033753
申请日：2020-09-26
申请人： Intel Corporation
发明人： Vivek Garg , Ankush Varma , Krishnakanth Sistla , Nikhil Gupta , Nikethan Shivanand Baligar , Stephen Wang , Nilanjan Palit , Timothy Kam , Adwait Purandare , Ujjwal Gupta , Stanley Chen , Dorit Shapira , Shruthi Venugopal , Suresh Chemudupati , Rupal Parikh , Eric Dehaemer , Pavithra Sampath , Phani Kumar Kandula , Yogesh Bansal , Dean Mulla , Michael Tulanowski , Stephen Haake , Andrew Herdrich , Ripan Das
摘要： Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.
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公开(公告)号：US09218046B2
公开(公告)日：2015-12-22
申请号：US14564436
申请日：2014-12-09
申请人： INTEL CORPORATION
CPC分类号： G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
摘要： An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
摘要翻译： 一种装置包括多个核心和耦合到核心的控制器。 如果基于与第二核心相关联的每个指令（CPI）的处理器时钟周期的第一数量高于第一阈值，则控制器将降低第一核心的工作点。 如果第一数量低于第二阈值，则控制器可操作以增加第一核心的工作点。
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公开(公告)号：US08775834B2
公开(公告)日：2014-07-08
申请号：US13791089
申请日：2013-03-08
申请人： Intel Corporation
CPC分类号： G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
摘要： An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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公开(公告)号：US08738942B2
公开(公告)日：2014-05-27
申请号：US13721794
申请日：2012-12-20
申请人： Intel Corporation
CPC分类号： G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
摘要： An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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公开(公告)号：US12093100B2
公开(公告)日：2024-09-17
申请号：US17033753
申请日：2020-09-26
申请人： Intel Corporation
发明人： Vivek Garg , Ankush Varma , Krishnakanth Sistla , Nikhil Gupta , Nikethan Shivanand Baligar , Stephen Wang , Nilanjan Palit , Timothy Yee-Kwong Kam , Adwait Purandare , Ujjwal Gupta , Stanley Chen , Dorit Shapira , Shruthi Venugopal , Suresh Chemudupati , Rupal Parikh , Eric Dehaemer , Pavithra Sampath , Phani Kumar Kandula , Yogesh Bansal , Dean Mulla , Michael Tulanowski , Stephen Paul Haake , Andrew Herdrich , Ripan Das , Nazar Syed Haider , Aman Sewani
CPC分类号： G06F1/28 , G06F1/30 , G06F13/20 , G06F2213/40
摘要： Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.
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