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公开(公告)号：US20210224070A1
公开(公告)日：2021-07-22
申请号：US17223103
申请日：2021-04-06
发明人： Thomas Anton LEYRER , William Cronin WALLACE , David Alston LIDE , Pratheesh Gangadhar THALAKKAL KOTTILAVEEDU
IPC分类号： G06F9/30 , G06F9/38 , G06F12/0875 , G06F9/48 , G06F30/34
摘要： A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.
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公开(公告)号：US20220164226A1
公开(公告)日：2022-05-26
申请号：US17666148
申请日：2022-02-07
IPC分类号： G06F9/48 , G06F16/9035 , G06F9/52 , G06F9/50 , G06F1/06 , G06F13/20 , G06F9/448 , G06F11/10 , H04L1/00 , G06F13/28 , G06F13/40
摘要： A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.
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公开(公告)号：US20240264865A1
公开(公告)日：2024-08-08
申请号：US18641544
申请日：2024-04-22
IPC分类号： G06F9/48 , G06F1/06 , G06F9/448 , G06F9/50 , G06F9/52 , G06F11/10 , G06F13/20 , G06F13/28 , G06F13/40 , G06F16/9035 , H04L1/00
CPC分类号： G06F9/4881 , G06F1/06 , G06F9/448 , G06F9/5011 , G06F9/5016 , G06F9/5038 , G06F9/52 , G06F11/1004 , G06F13/20 , G06F13/28 , G06F13/4068 , G06F16/9035 , H04L1/0041 , G06F2209/5012 , G06F2209/503
摘要： A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.
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公开(公告)号：US20210326178A1
公开(公告)日：2021-10-21
申请号：US17359749
申请日：2021-06-28
发明人： Thomas Anton LEYRER , William Cronin WALLACE , Pratheesh Gangadhar THALAKKAL KOTTILAVEEDU , David Alston LIDE
IPC分类号： G06F9/48 , G06F16/9035 , G06F9/52 , G06F9/50 , G06F1/06 , G06F13/20 , G06F9/448 , G06F11/10 , H04L1/00 , G06F13/28 , G06F13/40
摘要： A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.
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公开(公告)号：US20210103469A1
公开(公告)日：2021-04-08
申请号：US17126143
申请日：2020-12-18
IPC分类号： G06F9/48 , G06F16/9035 , G06F9/52 , G06F9/50 , G06F1/06 , G06F13/20 , G06F9/448 , G06F11/10 , H04L1/00 , G06F13/28 , G06F13/40
摘要： A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.
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