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公开(公告)号：US20210224070A1
公开(公告)日：2021-07-22
申请号：US17223103
申请日：2021-04-06
发明人： Thomas Anton LEYRER , William Cronin WALLACE , David Alston LIDE , Pratheesh Gangadhar THALAKKAL KOTTILAVEEDU
IPC分类号： G06F9/30 , G06F9/38 , G06F12/0875 , G06F9/48 , G06F30/34
摘要： A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.
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公开(公告)号：US20220214913A1
公开(公告)日：2022-07-07
申请号：US17699242
申请日：2022-03-21
IPC分类号： G06F9/48 , G06F16/9035 , G06F9/52 , G06F9/50 , G06F1/06 , G06F13/20 , G06F9/448 , G06F11/10 , H04L1/00 , G06F13/28 , G06F13/40
摘要： A task manager tightly coupled to a programmable real-time unit (PRU), the task manager configured to: detect a first event; assert, a request to the PRU during a first clock cycle that the PRU perform a second task; receive an acknowledgement of the request from the PRU during the first clock cycle; save a first address in a memory during the first clock cycle of the PRU, the first address corresponding to a first task of the PRU, the first address present in a current program counter of the PRU; load a second address of the memory into a second program counter during the first clock cycle, the second address corresponding to the second task; and load, during a second clock cycle, the second address into the current program counter, wherein the second clock cycle immediately follows the first clock cycle.
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3.发明申请公开(公告)号：US20200059311A1
公开(公告)日：2020-02-20
申请号：US16552353
申请日：2019-08-27
IPC分类号： H04J3/06
摘要： A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.
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4.发明申请公开(公告)号：US20220286412A1
公开(公告)日：2022-09-08
申请号：US17751774
申请日：2022-05-24
IPC分类号： H04L49/25 , G05B19/4155 , H04L43/16 , H04L45/74
摘要： An ultra-high speed electronic communications device includes: a network communications interface; a memory; and one or more processing units, communicatively coupled to the memory and the network communications interface, wherein the memory stores instructions configured to cause the one or more processing units to: receive a data packet using the network communications interface; determine a classification of the data packet based, at least in part, on a plurality of factors, wherein the plurality of factors comprises a rate at which the data packet was received and a time at which the data packet was received; select, based at least in part, on the classification, an operation from a plurality of operations, wherein the plurality of operations comprises a cut-through operation and a store-and-forward operation; and perform the selected operation.
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公开(公告)号：US20220164226A1
公开(公告)日：2022-05-26
申请号：US17666148
申请日：2022-02-07
IPC分类号： G06F9/48 , G06F16/9035 , G06F9/52 , G06F9/50 , G06F1/06 , G06F13/20 , G06F9/448 , G06F11/10 , H04L1/00 , G06F13/28 , G06F13/40
摘要： A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.
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公开(公告)号：US20210028777A1
公开(公告)日：2021-01-28
申请号：US17066660
申请日：2020-10-09
摘要： An integrated communications subsystem (ICSS) includes a pulse-width modulator which drives a power stage, such as a motor. The pulse-width modulator is configured shut off the power stage when the pulse-width modulator receives a trip signal from a logic circuit of the ICSS. The logic circuit can easily be reprogrammed to send a trip signal only when certain error conditions are detected. Moreover, the ICSS contains one or more filters which can adjust the sensitivity of the logic circuit to error signals, enabling the ICSS to distinguish between true errors which require shutdown and glitches, which can be ignored during operation of the ICSS.
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公开(公告)号：US20240264865A1
公开(公告)日：2024-08-08
申请号：US18641544
申请日：2024-04-22
IPC分类号： G06F9/48 , G06F1/06 , G06F9/448 , G06F9/50 , G06F9/52 , G06F11/10 , G06F13/20 , G06F13/28 , G06F13/40 , G06F16/9035 , H04L1/00
CPC分类号： G06F9/4881 , G06F1/06 , G06F9/448 , G06F9/5011 , G06F9/5016 , G06F9/5038 , G06F9/52 , G06F11/1004 , G06F13/20 , G06F13/28 , G06F13/4068 , G06F16/9035 , H04L1/0041 , G06F2209/5012 , G06F2209/503
摘要： A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.
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8.发明申请公开(公告)号：US20220368444A1
公开(公告)日：2022-11-17
申请号：US17876662
申请日：2022-07-29
IPC分类号： H04J3/06
摘要： A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.
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公开(公告)号：US20210326178A1
公开(公告)日：2021-10-21
申请号：US17359749
申请日：2021-06-28
发明人： Thomas Anton LEYRER , William Cronin WALLACE , Pratheesh Gangadhar THALAKKAL KOTTILAVEEDU , David Alston LIDE
IPC分类号： G06F9/48 , G06F16/9035 , G06F9/52 , G06F9/50 , G06F1/06 , G06F13/20 , G06F9/448 , G06F11/10 , H04L1/00 , G06F13/28 , G06F13/40
摘要： A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.
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公开(公告)号：US20210103469A1
公开(公告)日：2021-04-08
申请号：US17126143
申请日：2020-12-18
IPC分类号： G06F9/48 , G06F16/9035 , G06F9/52 , G06F9/50 , G06F1/06 , G06F13/20 , G06F9/448 , G06F11/10 , H04L1/00 , G06F13/28 , G06F13/40
摘要： A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.
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