公开(公告)号：US09602443B2

公开(公告)日：2017-03-21

申请号：US14557020

申请日：2014-12-01

申请人： Intel Corporation

发明人： Linden Cornett ,  David B. Minturn ,  Sujoy Sen ,  Hemal V. Shah ,  Anshuman Thakur ,  Gary Tsao ,  Anil Vasudevan

IPC分类号： H04L12/54 ,  H04L12/861 ,  H04L12/863 ,  H04L29/06

CPC分类号： H04L49/9042 ,  H04L47/50 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163

摘要： In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

公开(公告)号：US12038858B2

公开(公告)日：2024-07-16

申请号：US17067334

申请日：2020-10-09

申请人： Intel Corporation

发明人： Anshuman Thakur ,  Dheeraj Subareddy ,  Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Mahesh Kumashikar ,  Sandeep Sane

IPC分类号： G06F13/20 ,  G06F13/40 ,  H01L25/16

CPC分类号： G06F13/20 ,  G06F2213/40

摘要： A processor package module comprises a substrate, one or more compute die mounted to the substrate, and one or more photonic die mounted to the substrate. The photonic die have N optical I/O links to transmit and receive optical I/O signals using a plurality of virtual optical channels, the N optical I/O links corresponding to different types of I/O interfaces excluding power and ground I/O. The substrate is mounted into a socket that support the power and ground I/O and electrical connections between the one or more compute die and the one or more photonic die.

公开(公告)号：US11657781B2

公开(公告)日：2023-05-23

申请号：US17256558

申请日：2019-03-01

申请人： Intel Corporation

发明人： Anshuman Thakur ,  DongHo Hong ,  Karthik Veeramani ,  Arvind Tomar ,  Brent Insko ,  Atsuo Kuwahara ,  Zhengmin Li

IPC分类号： G09G5/12 ,  G06T1/20 ,  G09G5/00 ,  G02B27/01 ,  G06F3/14 ,  A63F13/26

CPC分类号： G09G5/12 ,  G02B27/017 ,  G06F3/1431 ,  G06T1/20 ,  G09G5/001 ,  G09G5/003 ,  G09G5/006 ,  A63F13/26 ,  A63F2300/8082 ,  G09G2360/18 ,  G09G2370/12 ,  G09G2370/16

摘要： Computers for supporting multiple virtual reality (VR) display devices and related methods are described herein. An example computer includes a graphics processing unit (GPU) to render frames for a first VR display device and a second VR display device, a memory to store frames rendered by the GPU for the first VR display device and the second VR display device, and a vertical synchronization (VSYNC) scheduler to transmit alternating first and second VSYNC signals to the GPU such that a time period between each of the first or second VSYNC signals and a subsequent one of the first or second VSYNC signals is substantially the same. The GPU is to, based on the first and second VSYNC signals, alternate between rendering a frame for the first VR display device and a frame for the second VR display device.

公开(公告)号：US20220011811A1

公开(公告)日：2022-01-13

申请号：US17484399

申请日：2021-09-24

申请人： Intel Corporation

发明人： Dheeraj Subbareddy ,  Anshuman Thakur ,  Atul Maheshwari ,  Mahesh Kumashikar ,  MD Altaf Hossain ,  Ankireddy Nalamalpu

IPC分类号： G06F1/12 ,  G06F9/30

摘要： A semiconductor device may include a programmable fabric and a processor. The processor may utilize one or more extension architectures. At least one of these extension architectures may be used to integrate and/or embed the programmable fabric into the processor as part of the processor. Systems and methods for transitioning data between the programmable fabric and the processor associated with different clock domains is described.

公开(公告)号：US12007929B2

公开(公告)日：2024-06-11

申请号：US17067365

申请日：2020-10-09

申请人： Intel Corporation

发明人： Anshuman Thakur ,  Dheeraj Subbareddy ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Mahesh Kumashikar

IPC分类号： G06F13/40

CPC分类号： G06F13/4068

摘要： A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path.

公开(公告)号：US11983135B2

公开(公告)日：2024-05-14

申请号：US17033593

申请日：2020-09-25

申请人： Intel Corporation

发明人： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Anshuman Thakur ,  Md Altaf Hossain ,  Mahesh Kumashikar ,  Kemal Aygün ,  Casey Thielen ,  Daniel Klowden ,  Sandeep B. Sane

IPC分类号： G06F13/42 ,  G06F30/30 ,  G06F30/347

CPC分类号： G06F13/4221 ,  G06F13/4282 ,  G06F30/30 ,  G06F30/347 ,  G06F2213/0026

摘要： Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.

公开(公告)号：US10388255B2

公开(公告)日：2019-08-20

申请号：US16024153

申请日：2018-06-29

申请人： Intel Corporation

发明人： Anshuman Thakur ,  DongHo Hong ,  Karthik Veeramani ,  Arvind Tomar ,  Brent Insko ,  Atsuo Kuwahara ,  Zhengmin Li

IPC分类号： G09G5/12 ,  A63F13/26 ,  G06T1/20 ,  G09G5/00 ,  G02B27/01

摘要： Computers for supporting multiple virtual reality (VR) display devices and related methods are described herein. An example computer includes a graphics processing unit (GPU) to render frames for a first VR display device and a second VR display device, a memory to store frames rendered by the GPU for the first VR display device and the second VR display device, and a vertical synchronization (VSYNC) scheduler to transmit alternating first and second VSYNC signals to the GPU such that a time period between each of the first or second VSYNC signals and a subsequent one of the first or second VSYNC signals is substantially the same. The GPU is to, based on the first and second VSYNC signals, alternate between rendering a frame for the first VR display device and a frame for the second VR display device.

公开(公告)号：US20180159803A1

公开(公告)日：2018-06-07

申请号：US15832195

申请日：2017-12-05

申请人： Intel Corporation

发明人： Linden Cornett ,  David B. Minturn ,  Sujoy Sen ,  Hemal V. Shah ,  Anshuman Thakur ,  Gary Y. Tsao ,  Anil Vasudevan

IPC分类号： H04L12/861 ,  H04L29/06 ,  H04L12/863

CPC分类号： H04L49/9042 ,  H04L47/50 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163

摘要： In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

公开(公告)号：US10015117B2

公开(公告)日：2018-07-03

申请号：US14803006

申请日：2015-07-17

申请人： Intel Corporation

发明人： Linden Cornett ,  David B. Minturn ,  Sujoy Sen ,  Hemal V. Shah ,  Anshuman Thakur ,  Gary Tsao ,  Anil Vasudevan

IPC分类号： H04L12/28 ,  H04L12/861 ,  H04L12/863 ,  H04L29/06

CPC分类号： H04L49/9042 ,  H04L47/50 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163

摘要： In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

公开(公告)号：US20150326509A1

公开(公告)日：2015-11-12

申请号：US14803006

申请日：2015-07-17

申请人： Intel Corporation

发明人： Linden Cornett ,  David B. Minturn ,  Sujoy Sen ,  Hemal V. Shah ,  Anshuman Thakur ,  Gary Tsao ,  Anil Vasudevan

IPC分类号： H04L12/861 ,  H04L12/863 ,  H04L29/06

CPC分类号： H04L49/9042 ,  H04L47/50 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163

摘要： In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

摘要翻译： 在一个实施例中，提供了一种方法。 该实施例的方法提供了将分组报头存储在被分配用于存储分组报头的至少一页存储器的集合上，并且将分组报头和分组有效载荷存储在不在分配的至少一页存储器的集合中的位置 以存储分组报头。