公开(公告)号：US20240340624A1

公开(公告)日：2024-10-10

申请号：US18297283

申请日：2023-04-07

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Alexandra M. Isaly ,  Wesley Ip ,  Zachary A. Silverstein ,  Logan Bailey

IPC分类号： H04W4/80 ,  H04B5/00 ,  H04L49/90 ,  H04W76/14

CPC分类号： H04W4/80 ,  H04B5/72 ,  H04L49/9042 ,  H04W76/14

摘要： Described are techniques for caching a data payload on a peripheral device for delivery to a target device. The techniques include receiving, at a peripheral device via a short-range wireless protocol, a data payload intended for a target device, where the data payload is received from a source device configured to send the data payload to the target device. The techniques further include storing the data payload in a memory of the peripheral device for a time that allows the peripheral device to be placed in network proximity of the target device and transfer the data payload from the peripheral device to the target device. The techniques further include detecting the target device via a short-range wireless network, and sending the data payload to the target device via a short-range wireless protocol used by the target device.

公开(公告)号：US20240015109A1

公开(公告)日：2024-01-11

申请号：US17810856

申请日：2022-07-06

申请人： CHECK POINT SOFTWARE TECHNOLOGIES LTD.

发明人： Oren Markovitz

IPC分类号： H04L47/62 ,  H04L47/52 ,  H04L49/90 ,  H04L49/901

CPC分类号： H04L47/621 ,  H04L47/522 ,  H04L49/9042 ,  H04L49/901

摘要： A method and device are presented for decreasing processing cycles spent forwarding packets of a communication from receive queues to at least one transmit queue of a network interface controller. When received, packets are placed into a receive queue based on property(ies) of a leading packet. Buffer metadata including transmit information is associated with each communication. Processor circuitry transfers the packets from each of the receive queues to a transmit queue and the buffer metadata is used to determine how to transmit the packet and how to process the packet before transmission.

公开(公告)号：US11838196B2

公开(公告)日：2023-12-05

申请号：US15930177

申请日：2020-05-12

申请人： Quad Miners

发明人： Jae Wan Hong ,  Young Jin Park

IPC分类号： H04L43/16 ,  H04L43/0876 ,  H04L69/22 ,  H04L43/06 ,  H04L67/1097 ,  H04L43/0817 ,  G06F12/0866 ,  H04L49/90 ,  H04L9/40 ,  H04L43/04

CPC分类号： H04L43/16 ,  G06F12/0866 ,  H04L43/04 ,  H04L43/06 ,  H04L43/0817 ,  H04L43/0876 ,  H04L49/9042 ,  H04L63/12 ,  H04L63/1416 ,  H04L63/1466 ,  H04L67/1097 ,  H04L69/22

摘要： A high performance packet stream storage method. Original packet data from data traffic transmitted over a network is collected. Collected original packet data is written in a memory. Metadata from the collected original package data is extracted and metadata is written in the memory. The original packet data and the metadata is stored in a storage unit.

公开(公告)号：US20180159803A1

公开(公告)日：2018-06-07

申请号：US15832195

申请日：2017-12-05

申请人： Intel Corporation

发明人： Linden Cornett ,  David B. Minturn ,  Sujoy Sen ,  Hemal V. Shah ,  Anshuman Thakur ,  Gary Y. Tsao ,  Anil Vasudevan

IPC分类号： H04L12/861 ,  H04L29/06 ,  H04L12/863

CPC分类号： H04L49/9042 ,  H04L47/50 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163

摘要： In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

公开(公告)号：US20180159802A1

公开(公告)日：2018-06-07

申请号：US15883465

申请日：2018-01-30

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Yalin BAO

IPC分类号： H04L12/861 ,  H04L12/721 ,  H04L12/883 ,  H04L12/773 ,  H04L12/879 ,  H04L12/873

CPC分类号： H04L49/9036 ,  H04L45/566 ,  H04L45/60 ,  H04L47/52 ,  H04L47/6275 ,  H04L49/109 ,  H04L49/901 ,  H04L49/9015 ,  H04L49/9021 ,  H04L49/9042

摘要： The disclosure describes a data enqueuing method. The method may include: receiving a to-be-enqueued data packet, dividing the data packet into several slices to obtain slice information of the slices, and marking a tail slice of the data packet with a tail slice identifier; enqueuing corresponding slice information according to an order of the slices in the data packet, and in a process of enqueuing the corresponding slice information, if a slice is marked with the tail slice identifier, determining that the slice is the tail slice of the data packet, and generating a first-type node; and determining whether a target queue is empty, and if the target queue is empty, writing slice information of the tail slice into the target queue, and updating a head pointer of a queue head list according to the first-type node.

公开(公告)号：US09985896B2

公开(公告)日：2018-05-29

申请号：US14574335

申请日：2014-12-17

申请人： Nicira, Inc.

发明人： Teemu Koponen ,  Ethan J. Jackson

IPC分类号： H04L12/851 ,  G06F12/0811 ,  G06F12/128 ,  H04L12/911 ,  H04L12/861 ,  H04L12/715 ,  H04L12/751 ,  H04L12/741 ,  H04L12/721

CPC分类号： H04L47/2441 ,  G06F12/0811 ,  G06F12/128 ,  G06F2212/283 ,  G06F2212/69 ,  G06F2212/70 ,  H04L45/02 ,  H04L45/38 ,  H04L45/64 ,  H04L45/745 ,  H04L47/827 ,  H04L49/9042

摘要： Some embodiments provide a method for processing a packet received by a managed forwarding element. The method performs a series of packet classification operations based on header values of the received packet. The packet classifications operations determine a next destination of the received packet. When the series of packet classification operations specifies to send the packet to a network service that performs payload transformations on the packet, the method (1) assigns a service operation identifier to the packet that identifies the service operations for the network service to perform on the packet, (2) sends the packet to the network service with the service operation identifier, and (3) stores a cache entry for processing subsequent packets without the series of packet classification operations. The cache entry includes the assigned service operation identifier. The network service uses the assigned service operation identifier to process packets without performing its own classification operations.

公开(公告)号：US20170353403A1

公开(公告)日：2017-12-07

申请号：US15610909

申请日：2017-06-01

申请人： Marvell Israel (M.I.S.L) Ltd.

发明人： Rami ZEMACH ,  Dror BROMBERG

IPC分类号： H04L12/883 ,  G06F3/06 ,  G06F5/14 ,  H04L12/861 ,  H04L12/863

CPC分类号： H04L49/9015 ,  G06F3/0659 ,  H04L47/6245 ,  H04L49/103 ,  H04L49/9005 ,  H04L49/9026 ,  H04L49/9042 ,  H04L49/9078

摘要： A first memory device stores (i) a head part of a FIFO queue structured as a linked list (LL) of LL elements arranged in an order in which the LL elements were added to the FIFO queue and (ii) a tail part of the FIFO queue. A second memory device stores a middle part of the FIFO queue, the middle part comprising a LL elements following, in an order, the head part and preceding, in the order, the tail part. A queue controller retrieves LL elements in the head part from the first memory device, moves LL elements in the middle part from the second memory device to the head part in the first memory device prior to the head part becoming empty, and updates LL parameters corresponding to the moved LL elements to indicate storage of the moved LL elements changing from the second memory device to the first memory device.

公开(公告)号：US20170331881A1

公开(公告)日：2017-11-16

申请号：US15152369

申请日：2016-05-11

申请人： Microsoft Technology Licensing, LLC

发明人： Badrish Chandramouli ,  Jonathan D. Goldstein ,  Milos Nikolic

IPC分类号： H04L29/08 ,  H04L12/911 ,  H04L12/861

CPC分类号： H04L67/10 ,  G06F17/30442 ,  H04L47/82 ,  H04L49/9042 ,  H04L67/12

摘要： The techniques and systems described herein are directed to providing deep integration of digital signal processing (DSP) operations with a general-purpose query processor. The techniques and systems provide a unified query language for processing tempo-relational and signal data, provide mechanisms for defining DSP operators, and support incremental computation in both offline and online analysis. The techniques and systems include receiving streaming data, aggregating and performing uniformity processing to generate a uniform signal, and storing the uniform signal in a batched columnar representation. Data can be copied from the batched columnar representation to a circular buffer, where DSP operations are applied to the data. Incremental processing can avoid redundant processing. Improvements to the functioning of a computer are provided by reducing an amount of data that to be passed back and forth between separate query databases and DSP processors, and by reducing a latency of processing and/or memory usage.

公开(公告)号：US09787613B2

公开(公告)日：2017-10-10

申请号：US14755485

申请日：2015-06-30

申请人： AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

发明人： Mark David Griswold ,  Michael Hei-Lung Lau

IPC分类号： H04L12/28 ,  H04L12/861 ,  H04L12/935 ,  H04L12/873

CPC分类号： H04L49/9057 ,  H04L47/52 ,  H04L49/3072 ,  H04L49/9042

摘要： Continuing to integrate more aggregate bandwidth and higher radix into switch devices is an economic imperative because it creates value both for the supplier and customer in large data center environments which are an increasingly important part of the marketplace. While new silicon processes continue to shrink transistor and other chip feature dimensions, process technology cannot be relied upon as a key driver of power reduction. Transitioning from 28 nm to 16 nm is a special case where FinFET provides additional power scaling, but subsequent FinFET nodes are not expected to deliver as substantial of power reductions to meet the desired increases in integration. The disclosed switch architecture attacks the power consumption problem by controlling the rate at which power-consuming activities occur.

公开(公告)号：US09712442B2

公开(公告)日：2017-07-18

申请号：US14072744

申请日：2013-11-05

申请人： BROADCOM CORPORATION

发明人： David Wu ,  Darren Duane Neuman ,  Flaviu Dorin Turean ,  Rajesh Shankarrao Mamidwar ,  Anand Tongle ,  Predrag Kostic

IPC分类号： H04L12/879 ,  H04L12/861 ,  H04L12/747

CPC分类号： H04L45/742 ,  H04L49/901 ,  H04L49/9042 ,  H04L49/9047 ,  H04L49/9078

摘要： A system for efficient memory bandwidth utilization may include a depacketizer, a packetizer, and a processor core. The depacketizer may generate header information items from received packets, where the header information items include sufficient information for the processor core to process the packets without accessing the payloads from off-chip memory. The depacketizer may accumulate multiple payloads and may write the multiple payloads to the off-chip memory in a single memory transaction when a threshold amount of the payloads have been accumulated. The processor core may receive the header information items and may generate a single descriptor for accessing multiple payloads corresponding to the header information items from the off-chip memory. The packetizer may generate a header for each payload based at least on on-chip information and without accessing off-chip memory. Thus, the subject system provides efficient memory bandwidth utilization, e.g. at least by reducing the number of off-chip memory accesses.