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    Retransmission and memory consumption tracking of data packets in a network device
    1.
    发明授权
    Retransmission and memory consumption tracking of data packets in a network device 有权
    网络设备中数据包的重传和内存消耗跟踪

    公开(公告)号：US09426079B2

    公开(公告)日：2016-08-23

    申请号：US14042655

    申请日：2013-09-30

    Applicant: Broadcom Corporation

    Inventor： David Wu ,  Darren Duane Neuman ,  Flaviu Dorin Turean ,  Rajesh Shankarrao Mamidwar ,  Anand Tongle ,  Sanjeev Sood

    IPC: H04L12/807

    CPC classification number: H04L47/27

    Abstract: A method of handling retransmission and memory consumption tracking of data packets includes storing data packets from different data channels in respective transmitter ring buffers allocated to the data channels when the data packets are not marked for retransmission, and facilitating retransmission of data packets from a specified ring buffer corresponding to a retransmission sequence number. The method also may include storing received data packets out of sequence in respective receiver ring buffers, marking a descriptor indicating a tail location of the stored data packets, and reclaiming memory space in the ring buffer based on the marked descriptor. The method may include storing a payload address associated with received data packets, marking a descriptor associated with the payload address to indicate the stored data packets have been consumed for processing, and reclaiming memory space when a register contains an indication of the stored payload address based on the marked descriptor.

    Abstract translation: 一种处理数据分组的重传和存储器消耗跟踪的方法包括：当数据分组未被标记用于重传时，将分配给数据信道的各个发射机环形缓冲器中的不同数据信道的数据分组存储，并且便于从指定的振铃 对应于重传序列号的缓冲区。 该方法还可以包括将接收到的数据分组按顺序存储在相应的接收机环形缓冲器中，标记指示存储的数据分组的尾部位置的描述符，以及基于标记的描述符回收环形缓冲器中的存储器空间。 该方法可以包括存储与接收到的数据分组相关联的有效载荷地址，标记与有效载荷地址相关联的描述符以指示所存储的数据分组已被消耗用于处理，以及当寄存器包含基于所存储的有效载荷地址的指示时，回收存储器空间 在标记描述符上。

    Lossless switching of traffic in a network device
    2.
    发明授权
    Lossless switching of traffic in a network device 有权

    公开(公告)号：US10404624B2

    公开(公告)日：2019-09-03

    申请号：US14072745

    申请日：2013-11-05

    Applicant: BROADCOM CORPORATION

    Inventor： Predrag Kostic ,  Darren Duane Neuman ,  David Wu ,  Anand Tongle ,  Rajesh Shankarrao Mamidwar ,  Milomir Aleksic

    IPC: G06F15/173 ,  H04L12/931

    Abstract: A system for lossless switching of traffic in a network device may be implemented when a network switch is integrated into a gateway device, or with any other data source. A processor of the gateway device may receive queue depth information for queues of the network switch. The processor may prevent data from being transmitted to congested queues of the network switch, while allowing data to be transmitted to uncongested queues. In this manner, data loss can be avoided through the network switch for data sourced from the gateway device, such as audio-video data retrieved from a hard drive, audio-video data received from a tuner, etc. Furthermore, re-transmission at higher layers can be reduced. Since the subject system observes congestion for each individual queue, only traffic destined to that particular, congested, queue is affected, e.g. paused. Traffic to non-congested queues is not affected, regardless of traffic class or egress port.

    Efficient memory bandwidth utilization in a network device
    3.
    发明授权
    Efficient memory bandwidth utilization in a network device 有权

    公开(公告)号：US09712442B2

    公开(公告)日：2017-07-18

    申请号：US14072744

    申请日：2013-11-05

    Applicant: BROADCOM CORPORATION

    Inventor： David Wu ,  Darren Duane Neuman ,  Flaviu Dorin Turean ,  Rajesh Shankarrao Mamidwar ,  Anand Tongle ,  Predrag Kostic

    IPC: H04L12/879 ,  H04L12/861 ,  H04L12/747

    CPC classification number: H04L45/742 ,  H04L49/901 ,  H04L49/9042 ,  H04L49/9047 ,  H04L49/9078

    Abstract: A system for efficient memory bandwidth utilization may include a depacketizer, a packetizer, and a processor core. The depacketizer may generate header information items from received packets, where the header information items include sufficient information for the processor core to process the packets without accessing the payloads from off-chip memory. The depacketizer may accumulate multiple payloads and may write the multiple payloads to the off-chip memory in a single memory transaction when a threshold amount of the payloads have been accumulated. The processor core may receive the header information items and may generate a single descriptor for accessing multiple payloads corresponding to the header information items from the off-chip memory. The packetizer may generate a header for each payload based at least on on-chip information and without accessing off-chip memory. Thus, the subject system provides efficient memory bandwidth utilization, e.g. at least by reducing the number of off-chip memory accesses.

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