公开(公告)号：US20160268418A1

公开(公告)日：2016-09-15

申请号：US15165372

申请日：2016-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoung-jae Lee ,  Seong-ho Cho ,  Ho-jung Kim ,  Young-soo Park ,  David Seo ,  In-kyeong Yoo

IPC: H01L29/788 ,  G11C16/04 ,  H01L27/115 ,  G11C14/00 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/788 ,  G06N3/049 ,  G06N3/063 ,  G11C11/54 ,  G11C11/5685 ,  G11C13/0007 ,  G11C14/0063 ,  G11C16/0433 ,  G11C2213/15 ,  G11C2213/53 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/408 ,  H01L29/42324 ,  H01L29/51 ,  H01L29/512 ,  H01L29/517 ,  H01L29/685 ,  H01L29/78 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/147

Abstract: Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic.

公开(公告)号：US09299789B2

公开(公告)日：2016-03-29

申请号：US13943006

申请日：2013-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： David Seo ,  Ho-jung Kim ,  Hyun-jong Chung ,  Seong-jun Park ,  Kyung-eun Byun ,  Hyun-jae Song ,  Jin-seong Heo

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/772 ,  H01L29/872 ,  H01L29/88 ,  H01L29/40

CPC classification number: H01L29/1606 ,  H01L29/407 ,  H01L29/66977 ,  H01L29/772 ,  H01L29/872 ,  H01L29/88

Abstract: A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element.

Abstract translation: 存储器件包括具有源电极，漏电极和栅电极的石墨烯开关器件。 石墨烯开关器件包括形成在漏电极和沟道之间的从源电极朝向漏电极的方向上的肖特基势垒。 存储器件不需要包括额外的存储元件。

公开(公告)号：US10141407B2

公开(公告)日：2018-11-27

申请号：US14506041

申请日：2014-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： David Seo ,  Ho-jung Kim ,  In-kyeong Yoo ,  Myoung-jae Lee ,  Seong-ho Cho

IPC: H01L27/108 ,  H01L29/66 ,  H01L45/00 ,  H01L29/16 ,  H01L29/68 ,  H01L27/105 ,  H01L29/76

Abstract: According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer.

公开(公告)号：US09379319B2

公开(公告)日：2016-06-28

申请号：US14444083

申请日：2014-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoung-jae Lee ,  Seong-ho Cho ,  Ho-jung Kim ,  Young-soo Park ,  David Seo ,  In-kyeong Yoo

IPC: H01L29/02 ,  H01L45/00 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C11/56 ,  G11C13/00

CPC classification number: H01L29/788 ,  G06N3/049 ,  G06N3/063 ,  G11C11/54 ,  G11C11/5685 ,  G11C13/0007 ,  G11C14/0063 ,  G11C16/0433 ,  G11C2213/15 ,  G11C2213/53 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/408 ,  H01L29/42324 ,  H01L29/51 ,  H01L29/512 ,  H01L29/517 ,  H01L29/685 ,  H01L29/78 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/147

Abstract: Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic.

Abstract translation: 提供了非易失性存储晶体管和包括非易失性存储晶体管的器件。 非易失性存储晶体管可以包括沟道元件，对应于沟道元件的栅极电极，沟道元件和栅电极之间的栅极绝缘层，栅极绝缘层和栅电极之间的离子物质移动层，以及源极 以及相对于沟道元件彼此分离的漏极。 根据施加到栅电极的电压，发生离子物质移动层处的离子物质的运动。 阈值电压根据离子物质的运动而变化。 非易失性存储晶体管具有多电平特性。

公开(公告)号：US10554994B2

公开(公告)日：2020-02-04

申请号：US16043851

申请日：2018-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-jung Kim ,  U-in Chung ,  Hyun-sik Choi

IPC: H04N19/50 ,  G11C11/41 ,  G11C14/00 ,  H03K19/177 ,  G11C29/02 ,  H04N19/17

Abstract: A logic device includes: a function block and a configuration block. The function block is configurable to perform operations associated with a plurality of operation modes. The configuration block is configured to configure the function block to perform an operation associated with any one of the plurality of operation modes. The logic device also includes a controller configured to control the configuration block so that the function block is configured to perform the operation.

公开(公告)号：US10051265B2

公开(公告)日：2018-08-14

申请号：US13963015

申请日：2013-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-jung Kim ,  U-in Chung ,  Hyun-sik Choi

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N19/593 ,  G11C14/00 ,  H03K19/177 ,  G11C11/41 ,  G11C29/02

CPC classification number: H04N19/50 ,  G11C11/41 ,  G11C14/009 ,  G11C29/028 ,  H03K19/17748 ,  H03K19/17772 ,  H03K19/17776 ,  H04N19/17

Abstract: A logic device includes: a function block and a configuration block. The function block is configurable to perform operations associated with a plurality of operation modes. The configuration block is configured to configure the function block to perform an operation associated with any one of the plurality of operation modes. The logic device also includes a controller configured to control the configuration block so that the function block is configured to perform the operation.

公开(公告)号：US09196340B2

公开(公告)日：2015-11-24

申请号：US14080108

申请日：2013-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-jung Kim ,  Hyun-sik Choi

IPC: G11C11/00 ,  G11C11/16 ,  H01L43/08 ,  H01L27/22 ,  G11C11/15 ,  H01L43/12

CPC classification number: G11C11/1675 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1673 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic random access memory (MRAM), and methods of manufacturing and operating the MRAM, include a switching element and a storage node connected to the switching element, and a magnetic node configured to simultaneously store two opposite bits.

Abstract translation: 磁性随机存取存储器（MRAM）以及制造和操作MRAM的方法包括连接到开关元件的开关元件和存储节点，以及被配置为同时存储两个相对的位的磁性节点。

公开(公告)号：US09172356B2

公开(公告)日：2015-10-27

申请号：US13688484

申请日：2012-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-sik Choi ,  Ho-jung Kim ,  Jai-kwang Shin ,  U-in Chung

IPC: H03B1/00 ,  H03K3/00 ,  G05F3/02 ,  H03K17/06

CPC classification number: H03K3/00 ,  G05F3/02 ,  H01L2924/0002 ,  H03K17/06 ,  H01L2924/00

Abstract: A high side gate driver, a switching chip, and a power device, which respectively include a protection device, are provided. The high side gate driver includes a first terminal configured to receive a first low level driving power supply that is provided to turn off the high side normally-on switch; a first switching device connected to the first terminal; and a protection device connected in series between the first switching device and a gate of the high side normally-on switch, the protection device configured to absorb a majority of a voltage applied to a gate of the high side normally-on switch. The power device includes the high side gate driver. In addition, the switching chip includes a high side normally-on switch, an additional normally-on switch, and a low side normally-on switch, which have a same structure.

Abstract translation: 提供分别包括保护装置的高侧栅极驱动器，开关芯片和功率器件。 高侧栅极驱动器包括：第一端子，被配置为接收被提供以关闭高侧常开开关的第一低电平驱动电源; 连接到第一端子的第一开关装置; 以及保护装置，串联连接在第一开关装置和高侧常开开关的栅极之间，保护装置被配置为吸收施加到高侧常开开关的栅极的电压的大部分。 功率器件包括高边栅驱动器。 此外，开关芯片包括具有相同结构的高边常开开关，附加常开开关和低边常开开关。

公开(公告)号：US09148150B2

公开(公告)日：2015-09-29

申请号：US13921642

申请日：2013-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-jung Kim ,  U-in Chung ,  Hyun-sik Choi

IPC: H01L25/00 ,  H03K19/177 ,  G06F17/50 ,  H03K19/173

CPC classification number: H03K19/173 ,  G06F17/5054 ,  H03K19/17728 ,  H03K19/17736

Abstract: A logic device includes first and second logic blocks and a connection block. Each of the first and second logic blocks configured to perform at least one function, the first logic blocks connected to first connection lines and the second logic blocks connected to second connection lines. The connection block electrically connected to the first and second logic blocks via the first connection lines and the second connection lines, respectively. The connection block including connection cells configured to select one of multiple connection configurations between the first connection lines and the second connection lines based on a desired function.

Abstract translation: 逻辑设备包括第一和第二逻辑块和连接块。 被配置为执行至少一个功能的第一和第二逻辑块中的每一个，连接到第一连接线的第一逻辑块和连接到第二连接线的第二逻辑块。 连接块分别经由第一连接线和第二连接线电连接到第一和第二逻辑块。 所述连接块包括被配置为基于期望功能在所述第一连接线和所述第二连接线之间选择多个连接配置中的一个的连接单元。

公开(公告)号：US09088151B2

公开(公告)日：2015-07-21

申请号：US13737217

申请日：2013-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-jung Kim ,  Jai-kwang Shin ,  U-in Chung ,  Hyun-sik Choi

IPC: G05F3/02 ,  G01F1/10 ,  H02H9/02 ,  H03K17/56 ,  H03K17/16

CPC classification number: H02H9/02 ,  H01L2924/0002 ,  H03K17/165 ,  H03K17/56 ,  H03K2217/0036 ,  H01L2924/00

Abstract: A power module including a power device and a periphery circuit configured to suppress a leakage current in the power device. The periphery circuit includes a leakage current detection circuit configured to detect a leakage current from the power device and control operation of the power device based on a result of the detection. The leakage current detection circuit including an input terminal connected to the power device, a plurality of NMOS transistors, a plurality of PMOS transistors connected to the plurality of NMOS transistors, and a comparator.

Abstract translation: 一种功率模块，包括功率器件和外围电路，被配置为抑制功率器件中的漏电流。 周边电路包括漏电流检测电路，其被配置为基于检测结果检测来自功率器件的漏电流和功率器件的控制操作。 泄漏电流检测电路包括连接到功率器件的输入端子，多个NMOS晶体管，连接到多个NMOS晶体管的多个PMOS晶体管和比较器。