公开(公告)号：US20240363764A1

公开(公告)日：2024-10-31

申请号：US18768737

申请日：2024-07-10

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kyongsik Yeom ,  Youngcheon Jeong ,  Yongkyu Lee

IPC分类号： H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H10B41/35 ,  H10B41/41

CPC分类号： H01L29/788 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/6656 ,  H01L29/66825 ,  H10B41/35 ,  H10B41/41

摘要： An integrated circuit includes: a source region, split gate structures on opposing sides of the source region, the split gate structures including a floating gate electrode layer and a control gate electrode layer, an erase gate structure between the split gate structures on the source region and including an erase gate electrode layer, a pair of selection gate structures on outer sidewalls of the split gate structures, and a pair of gate spacers. Each gate spacer is disposed between one of the split gate structures and one of the selection gate structures, includes a first gate spacer and a second gate spacer disposed on the first gate spacer, and is further disposed on an outer side wall of the one of the split gate structures. A lowermost end of the second gate spacer is at a lower level than an upper surface of the floating gate electrode layer.

公开(公告)号：US20240363763A1

公开(公告)日：2024-10-31

申请号：US18771108

申请日：2024-07-12

申请人： Micron Technology, Inc.

发明人： Kamal M. Karda ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/78696 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/823412 ,  H01L29/66666 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/7869

摘要： A device comprises a vertical transistor and a shielding material comprising a conductive material having a P+ type conductivity. The vertical transistor includes an electrode, a dielectric material adjacent to the electrode, and a channel region adjacent to the dielectric material. The channel region comprises a composite structure including at least two semiconductor materials. Also disclosed is a device comprising a first electrically conductive line, vertical transistors overlying the first conductive line, a second electrically conductive line overlying the vertical transistors, and a shielding material positioned between the two adjacent vertical transistors. Each of the vertical transistors comprises a gate electrode, a gate dielectric material on opposite sides of the gate electrode, and a channel region comprising a composite structure including at least two oxide semiconductor materials. The gate dielectric material positions between the gate electrode and the channel region. The shielding material comprises an electrically conductive material.

公开(公告)号：US20240363759A1

公开(公告)日：2024-10-31

申请号：US18768357

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/78612 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0921 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor device according to the present disclosure includes an active region including a channel region and a source/drain region adjacent the channel region, a vertical stack of channel members over the channel region, a gate structure over and around the vertical stack of channel members, a bottom dielectric feature over the source/drain region, a source/drain feature over the bottom dielectric feature, and a germanium layer disposed between the bottom dielectric feature and the source/drain region.

公开(公告)号：US20240363736A1

公开(公告)日：2024-10-31

申请号：US18770792

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Su-Hao Liu ,  Huicheng Chang ,  Chien-Tai Chan ,  Liang-Yin Chen ,  Yee-Chia Yeo ,  Szu-Ying Chen

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/66818 ,  H01L21/823431 ,  H01L29/785

摘要： The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.

公开(公告)号：US20240363725A1

公开(公告)日：2024-10-31

申请号：US18309125

申请日：2023-04-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Ling Hsieh ,  Hung-Ju Chou ,  Yu-Shan Lu ,  Wei-Yang Lee ,  Chih-Chung Chang ,  Yao-Hsuan Lai

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC分类号： H01L29/66439 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775

摘要： Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes forming a semiconductor fin over a substrate, forming an integral dielectric layer over the substrate, wherein the dielectric layer includes a first portion extending along a sidewall surface of the semiconductor fin and a second portion disposed over the semiconductor fin, a thickness of the second portion of the dielectric layer is greater than a thickness of the first portion of the dielectric layer, forming a dummy gate electrode layer over the substrate, patterning the dielectric layer and the dummy gate electrode layer to form a dummy gate structure over a channel region of the semiconductor fin, forming source/drain features coupled to the channel region of the semiconductor fin and adjacent to the dummy gate structure, and replacing the dummy gate structure with a gate stack.

公开(公告)号：US20240363724A1

公开(公告)日：2024-10-31

申请号：US18307025

申请日：2023-04-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ding-Kang Shih

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC分类号： H01L29/66439 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775

摘要： A method of manufacturing a semiconductor device includes: forming a stack of semiconductor layers and sacrificial layers alternately arranged over a substrate; patterning the stack to form a stacking structure on the substrate; disposing a sacrificial gate structure on the substrate, where the sacrificial gate structure covers a portion of the stacking structure; removing portions of the stacking structure not overlapped with the sacrificial gate structure; disposing source/drain regions at opposite sides of the sacrificial gate structure, where the semiconductor layers in the remained stacking structure connect between the source/drain regions; removing the sacrificial gate structure and rest of the sacrificial layers to form a cavity accessibly revealing the semiconductor layers; forming a semiconductor material to cover the semiconductor layers; performing a thermal process to transfer the semiconductor material into a Si-containing layer and a Ge-containing layer, where the Si-containing layer is disposed over the semiconductor layers, and the Ge-containing layer is interposed between the Si-containing layer and the semiconductor layers; and forming a gate structure in the cavity and over the remained stacking structure.

公开(公告)号：US20240363707A1

公开(公告)日：2024-10-31

申请号：US18769182

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wen HUANG ,  Chung-Ting KO ,  Hong-Hsien KE ,  Chia-Hui LIN ,  Tai-Chun HUANG

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/02063 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02343 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

摘要： A semiconductor device is provided. The semiconductor device includes a source/drain structure, a contact structure, a glue layer, a barrier layer, and a silicide layer. The contact structure is over the source/drain structure. The glue layer surrounds the contact structure. The barrier layer is formed on at least a portion of a sidewall surface of the contact structure. The silicide layer is between the source/drain structure and the contact structure, and the silicide layer is in direct contact with the glue layer. The bottom surface of the glue layer is lower than the top surface of the source/drain structure and the bottom surface of the barrier layer.

公开(公告)号：US20240363701A1

公开(公告)日：2024-10-31

申请号：US18492327

申请日：2023-10-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jongryeol Yoo

IPC分类号： H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： The present disclosure relates to semiconductor devices and their fabrication methods. One example semiconductor device comprises a substrate that includes an active region, an active pattern on the active region, a source/drain pattern on the active pattern, an active contact that extends from a top surface to a sidewall of the source/drain pattern and includes a first part that covers the sidewall of the source/drain pattern and a second part that covers the top surface of the source/drain pattern, a first layer between the source/drain pattern and the first part, and a second layer separated from the first layer and across the first part. Each of the first layer and the second layer includes a silicide layer.

公开(公告)号：US20240363690A1

公开(公告)日：2024-10-31

申请号：US18306421

申请日：2023-04-25

申请人： QUALCOMM Incorporated

发明人： Haining Yang ,  Ming-Huei Lin ,  Junjing Bao

IPC分类号： H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： Gate-all-around (GAA) field-effect transistor (FET) device employing strain material structure in inactive gate region(s) of a gate for applying channel strain to the channel(s) of the GAA FET for increased carrier mobility. The GAA FET device includes a GAA P-type (P) FET (PFET) and a GAA N-type (N) FET (NFET) served by a gate with a strain material in the inactive gate region(s) of the gate adjacent to the active gates of the GAA NFET and GAA PFET. In this manner, the strain material applies strain to both the GAA NFET and GAA PFET channels in the elongated direction of the gate in a direction orthogonal to their channel directions between the respective sources and drains, so that a strain material of the same strain type can be used to increase carrier mobility of both the GAA NFET and GAA PFET alike.

公开(公告)号：US20240363688A1

公开(公告)日：2024-10-31

申请号：US18764317

申请日：2024-07-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tse Hung ,  Ang-Sheng Chou ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Chao-Ching Cheng

IPC分类号： H01L29/10 ,  H01L23/36 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1033 ,  H01L23/36 ,  H01L29/0607 ,  H01L29/0669 ,  H01L29/66477 ,  H01L29/78

摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.