公开(公告)号：US20240363435A1

公开(公告)日：2024-10-31

申请号：US18766003

申请日：2024-07-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

摘要： The present disclosure provides a method that includes providing a workpiece having a semiconductor substrate that includes a first circuit area and a second circuit area, forming a first active region in the first circuit area and a second active region on the second circuit area, forming first gate stacks on the first active region and second gate stacks on the second active region, performing a plurality of implantation processes to introduce a doping species to the first active region with a first dosage and to the second active region with a second dosage different from the first dosage, and forming first source/drain features within first source/drain regions of the first active region and second source/drain features within second source/drain regions of the second active region.

公开(公告)号：US12100594B2

公开(公告)日：2024-09-24

申请号：US17595589

申请日：2021-03-12

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： ChihCheng Liu

IPC分类号： H01L21/033 ,  H01L21/265 ,  H01L21/266 ,  H10B12/00

CPC分类号： H01L21/0338 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/266 ,  H10B12/00

摘要： An active region array formation method is provided, including: providing a substrate, and forming a first hard mask layer on a surface of the substrate; patterning the first hard mask layer by using a composite etching process to form an active region shielding layer in the first hard mask layer, a pattern of the active region shielding layer being matched with a pattern of a to-be-formed active region array, wherein the composite etching process includes at least two patterning processes and at least one pattern transfer process; removing the remaining first hard mask layer; and forming the active region array in the substrate through the active region shielding layer.

公开(公告)号：US12087585B2

公开(公告)日：2024-09-10

申请号：US17362946

申请日：2021-06-29

申请人： Applied Materials, Inc.

发明人： Qintao Zhang ,  Samphy Hong ,  Wei Zou ,  Judy Campbell Soukup

IPC分类号： H01L21/00 ,  H01L21/265 ,  H01L21/266

CPC分类号： H01L21/26593 ,  H01L21/26533 ,  H01L21/266

摘要： Disclosed herein are methods for forming a buried layer using a low-temperature ion implant. In some embodiments a method may include providing an opening through a mask, wherein the mask is formed directly atop a substrate, and forming a buried layer in the substrate by performing a low-temperature ion implant through the opening of the mask. The method may further include forming an oxide layer over the substrate including over the buried layer.

公开(公告)号：US12080607B2

公开(公告)日：2024-09-03

申请号：US18321188

申请日：2023-05-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

摘要： The present disclosure provides a fabrication method that includes providing a workpiece having a semiconductor substrate with a first circuit area and a second circuit area; forming a first active region within the first circuit area and a second active region within the second circuit area; forming a first gate structure on the first active region and a second gate structure on the second active region; introducing a doping species to the first active region but not the second active region; performing an etching process, thereby simultaneously recessing both first source/drain regions of the first active region and second source/drain regions of the second active region at a same etch rate; and thereafter, epitaxially growing first source/drain features within the first source/drain regions and second source/drain features within the second source/drain regions.

公开(公告)号：US20240250170A1

公开(公告)日：2024-07-25

申请号：US18625798

申请日：2024-04-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC China Company Limited

发明人： Lian-Jie LI ,  Yan-Bin LU ,  Feng HAN ,  Shuai ZHANG

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/6659 ,  H01L29/66681 ,  H01L29/7816

摘要： A semiconductor device includes a gate structure, a drift region, a source region, a drain region, a first doped region, and a second doped region. The gate structure is over a semiconductor substrate. The drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. The source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. The drain region is in the drift region. The first doped region is in the drift region and between the drain region and the gate structure. The second doped region is within the drift region. The second doped region forms a P-N junction with the first doped region at a bottom surface of the first doped region.

公开(公告)号：US20240249980A1

公开(公告)日：2024-07-25

申请号：US18243501

申请日：2023-09-07

申请人： Adeia Semiconductor Solutions LLC

发明人： Kangguo Cheng

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00 ,  H10B12/00

CPC分类号： H01L21/823487 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76232 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/088 ,  H01L29/0603 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H10B10/12 ,  H10B12/36

摘要： A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

公开(公告)号：US20240243167A1

公开(公告)日：2024-07-18

申请号：US18411252

申请日：2024-01-12

申请人： Magnachip Semiconductor, Ltd.

发明人： Chanho PARK ,  Kihwan KIM ,  Jungyeon LEE ,  Suyoung MOON ,  Jiyong LIM

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266

CPC分类号： H01L29/0634 ,  H01L29/402 ,  H01L29/66666 ,  H01L29/7827 ,  H01L21/26513 ,  H01L21/266

摘要： A super junction semiconductor device includes a substrate, an active cell disposed on the substrate, an edge termination region surrounding the active cell, a peripheral region formed between the active cell and the edge termination region, a plurality of first conductivity type pillars and second conductivity type pillars alternately provided at an edge of the active cell and the peripheral region and the edge termination region, and a charge sharing region connecting the second conductivity type pillars in the peripheral region with the second conductivity type pillars in the edge termination region above the peripheral region and the edge termination region.

公开(公告)号：US12040366B2

公开(公告)日：2024-07-16

申请号：US17303809

申请日：2021-06-08

申请人： The Boeing Company

发明人： Kangmu Min Lee ,  Maxwell Daehan Choi ,  Jeffrey Alden Wright ,  Wonill Ha ,  Clayton Jackson ,  Michael Pemberton Jura ,  Adele Schmitz ,  James Chappell

IPC分类号： H01L29/06 ,  H01L21/04 ,  H01L21/265 ,  H01L21/762 ,  H01L29/40 ,  H01L29/417 ,  H01L21/266 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20

CPC分类号： H01L29/41766 ,  H01L21/0465 ,  H01L21/2652 ,  H01L21/26553 ,  H01L21/76232 ,  H01L29/401 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003

摘要： A method for forming a semiconductor structure. Two isolation structures are formed in a semiconductor. A cavity is etched in the semiconductor between the two isolation structures in the semiconductor. Dopants are implanted into a bottom side of the cavity to form a doped region in the semiconductor below the cavity between the two isolation structures. A contact is formed in the cavity. The contact is on the doped region and in direct contact with the doped region.

公开(公告)号：US20240234413A9

公开(公告)日：2024-07-11

申请号：US18452834

申请日：2023-08-21

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Natsumi IKEDA ,  Tohru KAWAI

IPC分类号： H01L27/06 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0629 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823462 ,  H01L21/823475 ,  H01L28/20 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/66492 ,  H01L29/7833

摘要： A semiconductor device including an oscillation circuit includes a MISFET having a halo region formed on a semiconductor substrate and a plurality of MISFETs having no halo regions formed on the semiconductor substrate. Gate electrodes of the plurality of MISFETs having no halo regions are electrically connected to each other. The plurality of MISFETs having no halo regions is used in a pair transistor included in the oscillation circuit.

公开(公告)号：US20240222489A1

公开(公告)日：2024-07-04

申请号：US18491600

申请日：2023-10-20

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai Cheng

IPC分类号： H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L29/20 ,  H01L29/66

CPC分类号： H01L29/7786 ,  H01L21/2654 ,  H01L21/266 ,  H01L29/2003 ,  H01L29/66462

摘要： The present disclosure provides a semiconductor structure, including a substrate, a channel layer, a barrier layer, and a P-type semiconductor layer that are distributed from bottom to top, where the barrier layer includes an Al element, and a variation curve of a proportion of Al element in the barrier layer is continuous; where at an interface between the channel layer and the barrier layer, the proportion of Al element in the barrier layer is the same as the proportion of Al element in the channel layer; and at an interface between the barrier layer and the P-type semiconductor layer, the proportion of Al element in the barrier layer is the same as the proportion of Al element in the P-type semiconductor layer.