公开(公告)号：US11923413B2

公开(公告)日：2024-03-05

申请号：US17666051

申请日：2022-02-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon-Jhy Liaw ,  Chao-Ching Cheng ,  Hung-Li Chiang ,  Shih-Syuan Huang ,  Tzu-Chiang Chen ,  I-Sheng Chen ,  Sai-Hooi Yeong

IPC分类号： H01L29/76 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L29/0673 ,  H01L21/02603 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.

公开(公告)号：US11804485B2

公开(公告)日：2023-10-31

申请号：US17304911

申请日：2021-06-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7851

摘要： Transistors of different types of electronic devices on the same semiconductor substrate are configured with different transistor attributes to increase the performance of the different types of electronic devices. Fin height, shallow source drain (SSD) height, source or drain width, and/or one or more other transistor attributes may be co-optimized for the different types of electronic devices by various semiconductor manufacturing processes such as etching, lithography, process loading, and/or masking, among other examples. This enables the performance of a plurality of types of electronic devices on the same semiconductor substrate to be increased.

公开(公告)号：US11728206B2

公开(公告)日：2023-08-15

申请号：US17583707

申请日：2022-01-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ta-Chun Lin ,  Tien-Shao Chuang ,  Kuang-Cheng Tai ,  Chun-Hung Chen ,  Chih-Hung Hsieh ,  Kuo-Hua Pan ,  Jhon-Jhy Liaw

IPC分类号： H01L27/088 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06

CPC分类号： H01L21/76232 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7851

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and an adjacent second fin structure protruding from the semiconductor substrate and an isolation structure formed in the semiconductor substrate and in direct contact with the first fin structure and the second fin structure. The first fin structure and the second fin structure each include a first portion protruding above a top surface of the isolation structure, a second portion in direct contact with a bottom surface of the first portion, and a third portion extending from a bottom of the second portion. A top width of the third portion is different than a bottom width of the third portion and a bottom width of the second portion.

公开(公告)号：US20210305421A1

公开(公告)日：2021-09-30

申请号：US17343776

申请日：2021-06-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Sheng Liang ,  Kuo-Hua Pan ,  Hsin-Che Chiang ,  Ming-Heng Tsai

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417

摘要： A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.

公开(公告)号：US20190103473A1

公开(公告)日：2019-04-04

申请号：US16206071

申请日：2018-11-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Hua Pan ,  Je-Wei Hsu ,  Hua Feng Chen ,  Jyun-Ming Lin ,  Chen-Huang Peng ,  Min-Yann Hsieh ,  Java Wu

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L29/08 ,  H01L21/311 ,  H01L29/78 ,  H01L29/45

摘要： A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

公开(公告)号：US09287276B2

公开(公告)日：2016-03-15

申请号：US13946819

申请日：2013-07-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shi-Wei Chang ,  Hong-Chen Cheng ,  Chien-Chi Tien ,  Li-Chun Tien ,  Kuo-Hua Pan ,  Jhon-Jhy Liaw

IPC分类号： H01L27/115 ,  H01L27/112 ,  G11C17/10

CPC分类号： H01L27/115 ,  G11C17/10 ,  H01L27/1122

摘要： A semiconductor memory cell array is disclosed that includes a memory cell unit. The memory cell unit includes an active region, a first transistor, a second transistor, a gate structure, and an interconnect. The first transistor and the second transistor are formed on the active region. The gate structure is formed on the active region and between the first transistor and the second transistor. The interconnect connects the gate structure and at least one of sources of the first transistor and the second transistor to a power line.

摘要翻译： 公开了一种包括存储单元单元的半导体存储单元阵列。 存储单元单元包括有源区，第一晶体管，第二晶体管，栅极结构和互连。 第一晶体管和第二晶体管形成在有源区上。 栅极结构形成在有源区和第一晶体管与第二晶体管之间。 互连将第一晶体管和第二晶体管的栅极结构和至少一个源极连接到电力线。

公开(公告)号：US08665654B2

公开(公告)日：2014-03-04

申请号：US13924176

申请日：2013-06-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hong-Chen Cheng ,  Ming-Yi Lee ,  Kuo-Hua Pan ,  Jung-Hsuan Chen ,  Li-Chun Tien ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C7/10

CPC分类号： G11C5/06 ,  G11C5/147 ,  G11C5/148 ,  G11C11/417

摘要： A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell.

摘要翻译： 存储器的列包括第一边缘单元和至少一个存储单元。 第一边缘单元位于列的第一边缘，并且包括第一边缘单元参考节点和第二边缘单元参考节点。 所述至少一个存储器单元中的每一个包括第一存储器参考节点。 第一边缘单元参考节点耦合到至少一个存储器单元的相应的第一存储器参考节点。 第二边缘单元参考节点用作至少一个存储单元的第二存储器参考节点。 第一边缘单元的前端层与至少一个存储单元的存储单元的前端层相同。

公开(公告)号：US20240363435A1

公开(公告)日：2024-10-31

申请号：US18766003

申请日：2024-07-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

摘要： The present disclosure provides a method that includes providing a workpiece having a semiconductor substrate that includes a first circuit area and a second circuit area, forming a first active region in the first circuit area and a second active region on the second circuit area, forming first gate stacks on the first active region and second gate stacks on the second active region, performing a plurality of implantation processes to introduce a doping species to the first active region with a first dosage and to the second active region with a second dosage different from the first dosage, and forming first source/drain features within first source/drain regions of the first active region and second source/drain features within second source/drain regions of the second active region.

公开(公告)号：US12080607B2

公开(公告)日：2024-09-03

申请号：US18321188

申请日：2023-05-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

摘要： The present disclosure provides a fabrication method that includes providing a workpiece having a semiconductor substrate with a first circuit area and a second circuit area; forming a first active region within the first circuit area and a second active region within the second circuit area; forming a first gate structure on the first active region and a second gate structure on the second active region; introducing a doping species to the first active region but not the second active region; performing an etching process, thereby simultaneously recessing both first source/drain regions of the first active region and second source/drain regions of the second active region at a same etch rate; and thereafter, epitaxially growing first source/drain features within the first source/drain regions and second source/drain features within the second source/drain regions.

公开(公告)号：US20240266224A1

公开(公告)日：2024-08-08

申请号：US18639739

申请日：2024-04-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ta-Chun Lin ,  Kuo-Hua Pan ,  Chih-Yung Lin ,  Jhon Jhy Liaw

IPC分类号： H01L21/8234 ,  H01L29/66

CPC分类号： H01L21/823431 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/6681

摘要： A method of forming a semiconductor structure includes forming a semiconductor fin over a substrate, forming a dummy gate stack over the semiconductor fin, depositing a dielectric layer over the dummy gate stack, and selectively etching the dielectric layer, such that a top portion and a bottom portion of the dielectric layer form a step profile. The method further includes removing portions of the dielectric layer to form a gate spacer and subsequently forming a source/drain feature in the semiconductor fin adjacent to the gate spacer.