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76 条记录 (耗时 0.017 秒)

    Nonvolatile semiconductor storage device with cell transistors
    2.
    发明授权
    Nonvolatile semiconductor storage device with cell transistors 有权

    公开(公告)号：US10700076B2

    公开(公告)日：2020-06-30

    申请号：US16177635

    申请日：2018-11-01

    申请人： ROHM Co., LTD.

    发明人： Kazuhisa Ukai ,  Koji Nigoriike

    IPC分类号： H01L27/112 ,  G11C7/06 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C17/10

    摘要： A nonvolatile semiconductor storage device includes a plurality of cell transistor pairs including a pair of cell transistors sharing a first node connected to a bit line or a source line, and a dummy gate line laid in parallel with gate lines of the cell transistors, the dummy gate line applying an off voltage to a dummy transistor between the cell transistor pairs. The gate lines and the dummy gate line may be laid at equal intervals. A plurality of impurity diffusion layers corresponding to the first node and second nodes of the cell transistors may be formed at equal intervals in a continuous active region.

    Circuit and/or method for implementing a patch mechanism for embedded program ROM
    5.
    发明授权
    Circuit and/or method for implementing a patch mechanism for embedded program ROM 有权

    公开(公告)号：US06891765B2

    公开(公告)日：2005-05-10

    申请号：US10634669

    申请日：2003-08-05

    申请人： Alon Saado

    发明人： Alon Saado

    IPC分类号： G06F9/445 ,  G06F11/00 ,  G06F12/06 ,  G11C7/00 ,  G11C16/04 ,  G11C16/10 ,  G11C17/00 ,  G11C17/10 ,  G11C29/00

    CPC分类号： G06F8/66 ,  G06F9/30181 ,  G06F12/0638 ,  G11C17/10

    摘要： The present invention concerns an apparatus comprising a memory, a logic circuit and a multiplexer. The memory generally comprises a first address space configured as read only and a second address space configured as read and write. The memory returns a first data item in response to a first address within the first address space. The logic circuit may be configured to (i) deassert a command signal in response to the first address not matching any of a plurality of predetermined addresses and (ii) generate a first branch instruction and assert the command signal in response to the first address matching one of the predetermined addresses in response to the matching. The multiplexer may be configured to select the first data item from the memory or the first branch instruction from the logic circuit in response to the command signal.

    Non-volatile read-only memory modifiable by redefinition of a metal or via level
    6.
    发明授权
    Non-volatile read-only memory modifiable by redefinition of a metal or via level 有权
    非易失性只读存储器可通过重新定义金属或通孔电平进行修改

    公开(公告)号：US06879506B2

    公开(公告)日：2005-04-12

    申请号：US10427713

    申请日：2003-05-01

    申请人： Philippe Lebourg ,  Davide Tesi

    发明人： Philippe Lebourg ,  Davide Tesi

    IPC分类号： G11C17/10 ,  H01L27/10 ,  G11C17/16 ,  G11C5/02 ,  G11C5/06

    CPC分类号： H01L27/101 ,  G11C17/10

    摘要： A memory element in an integrated circuit includes several levels of conductive materials separated by insulating levels, each of which is capable of being crossed by conductive vias of an intercalary via level, and at least two connection rails, including several assemblies of successive interconnected areas and vias, a first assembly being formed of a zigzag running from a first metal level to a last metal level and back to the first metal level between a first end and a second end, each of the other assemblies being connected to one of the connection rails, the first end of the zigzag being connected to an initial assembly among the other assemblies.

    摘要翻译： 集成电路中的存储元件包括由绝缘电平分开的几层导电材料，每层都能够穿过闰月通孔层的导电通孔，以及包括连续相互连接的区域的多个组件的至少两个连接轨道，以及 通孔，第一组件由从第一金属层到最后金属层之间的之字形形成，并且在第一端与第二端之间回到第一金属层，其它组件中的每一个连接到一个连接轨道 之字形的第一端连接到其他组件之间的初始组件。

    Word line driver in a multi-value mask ROM
    7.
    发明授权
    Word line driver in a multi-value mask ROM 失效
    字线驱动在多值掩码ROM中

    公开(公告)号：US5892727A

    公开(公告)日：1999-04-06

    申请号：US936732

    申请日：1997-09-25

    申请人： Yukiharu Nakagawa

    发明人： Yukiharu Nakagawa

    IPC分类号： G11C16/04 ,  G11C8/08 ,  G11C11/56 ,  G11C17/10 ,  G11C8/00

    CPC分类号： G11C17/10 ,  G11C11/56 ,  G11C11/5692 ,  G11C8/08 ,  G11C16/08 ,  G11C8/14

    摘要： A method for driving a word line in a multi-value mask ROM comprises the consecutive steps of precharging the word line by a source potential, setting the word line at a first potential which is lower than the source potential and reading data from a selected memory cell, precharging the word line by the source potential, charging the word line at the second potential which is lower than the source potential and reading data from the selected memory cell, setting the word line at the source potential and reading data from the selected memory cell. The precharge of the word line reduces the read time for the multi-value mask ROM.

    摘要翻译： 用于在多值掩模ROM中驱动字线的方法包括：将字线预先充电源电位的连续步骤，将字线设置在低于源电位的第一电位，并从所选存储器读取数据 单元，将字线预先充电源电位，在低于源极电位的第二电位对字线充电，并从所选择的存储单元读取数据，将字线设置为源极电位并从所选择的存储器读取数据 细胞。 字线的预充电减少了多值掩模ROM的读取时间。

    Semiconductor memory device with reduced probability of power consumption
    8.
    发明授权
    Semiconductor memory device with reduced probability of power consumption 失效
    具有降低功耗概率的半导体存储器件

    公开(公告)号：US5787033A

    公开(公告)日：1998-07-28

    申请号：US684209

    申请日：1996-07-19

    申请人： Hideshi Maeno

    发明人： Hideshi Maeno

    IPC分类号： G11C17/12 ,  H01L27/112 ,  G11C17/10

    CPC分类号： H01L27/112 ,  G11C17/12

    摘要： A programming of memory cells in an upper block (UB) is reversely made, thereby obtaining reverse data which are opposite to desired data when the upper block (UB) is selected. An inverter circuit (IV) is additionally provided at an output of a sense amplifier (SA1) and inverts the reverse data, thus eventually obtaining the desired data. Having such configuration as to reduce the number of ON/OFF controllable memory cells, a semiconductor memory device which cuts power consumption is provided. Moreover, with OFF-state memory cells having such configuration as to suppress application of load (charge) capacity to bit lines and word lines as much as possible, the semiconductor memory device which ensures high-speed access to the memory cells is provided.

    摘要翻译： 反向进行上部块（UB）中的存储器单元的编程，从而获得当选择上部块（UB）时与期望数据相反的反向数据。 反相器电路（IV）另外设置在读出放大器（SA1）的输出端并反相数据，从而最终获得期望的数据。 具有减少ON / OFF可控存储单元的数量的结构，提供了一种削减功耗的半导体存储器件。 此外，在具有尽可能地抑制对位线和字线的负载（电荷）容量的配置的关闭状态存储单元的情况下，提供了确保对存储单元的高速访问的半导体存储器件。

    Multi-stage ROM wherein a cell current of a selected memory cell is compared with a plurality of constant currents when driven to read voltages
    9.
    发明授权
    Multi-stage ROM wherein a cell current of a selected memory cell is compared with a plurality of constant currents when driven to read voltages 失效
    多级ROM，其中当被驱动读取电压时，所选存储单元的单元电流与多个恒定电流进行比较

    公开(公告)号：US5668752A

    公开(公告)日：1997-09-16

    申请号：US625994

    申请日：1996-04-01

    申请人： Kiyokazu Hashimoto

    发明人： Kiyokazu Hashimoto

    IPC分类号： G11C17/00 ,  G11C7/06 ,  G11C11/56 ,  G11C16/02 ,  G11C17/10

    CPC分类号： G11C11/5692 ,  G11C11/56 ,  G11C7/062 ,  G11C16/32 ,  G11C7/06

    摘要： For a nonvolatile multi-stage semiconductor memory device, a data reading sequence is given first, second, and third phases. During the first phase, a word line is driven to 2.25 V with a differential amplifier and a bias circuit activated to sense on or off of a selected memory cell. During the second phase, the word line is driven to 3.0 V with a differential amplifier and a bias circuit activated to sense on or off of the selected memory cell. This enables correct read out with a low operating voltage, such as 3.0 V, of data stored in semiconductor memory cells with a selected one of four threshold levels given to each datum. During the third phase, it is possible to use the differential amplifier and the bias circuit which are used during the first phase. Use of one differential amplifier alone is possible with two bias circuits used. Use of only first and second phases is also possible.

    摘要翻译： 对于非易失性多级半导体存储器件，给出第一，第二和第三相的数据读取序列。 在第一阶段期间，使用差分放大器将字线驱动到2.25V，并且激活偏置电路以感测选择的存储单元的导通或截止。 在第二阶段期间，使用差分放大器将字线驱动到3.0 V，并且激活偏置电路以感测所选择的存储单元的导通或关闭。 这使得能够以对每个数据给出的四个阈值电平中选择的一个来存储在半导体存储器单元中的数据的低工作电压（例如3.0V）进行正确读出。 在第三阶段期间，可以使用在第一阶段期间使用的差分放大器和偏置电路。 仅使用一个差分放大器就可以使用两个偏置电路。 仅使用第一和第二阶段也是可能的。

    Programmable bit cell
    10.
    发明授权
    Programmable bit cell 失效
    可编程位单元

    公开(公告)号：US5408428A

    公开(公告)日：1995-04-18

    申请号：US176811

    申请日：1994-01-03

    申请人： Bradley Burgess ,  Jeffrey Slaton

    发明人： Bradley Burgess ,  Jeffrey Slaton

    IPC分类号： G11C17/10 ,  H01L27/02 ,  G11C17/00

    CPC分类号： H01L23/544 ,  G11C17/10 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L27/02 ,  H01L2924/0002

    摘要： A mask-programmable read only memory bit cell (16) has a pair of conductive elements for each conductive layer in the integrated device but the last layer (30 and 34, 38 and 42, 46 and 50) and single conductive element in the last layer (54). The first and second elements in the first pair of elements receive a first and a second voltage supply (V.sub.DD and V.sub.GND), respectively. The single element outputs a voltage corresponding to the logic state stored by the bit cell. A plurality of pairs of conductive vias couple particular ones of the elements in each layer to particular ones of the elements in adjacent layers. The logic state stored by the bit cell may be reversed by reversing the connection of any one pair of elements and its associated vias. This makes the bit cell suitable for use in a processor version register.

    摘要翻译： 掩模可编程只读存储器位单元（16）具有用于集成器件中的每个导电层的一对导电元件，但是最后一层（30和34,38,42,46和50）和最后一层中的单个导电元件 层（54）。 第一对元件中的第一和第二元件分别接收第一和第二电压源（VDD和VGND）。 单个元件输出与位单元存储的逻辑状态对应的电压。 多对导电通孔将每个层中的特定元件与相邻层中的特定元件相结合。 由位单元存储的逻辑状态可以通过反转任何一对元件及其相关联的通孔的连接来反转。 这使得位单元适用于处理器版本寄存器。