公开(公告)号：US20140197450A1

公开(公告)日：2014-07-17

申请号：US13740805

申请日：2013-01-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： CHIEH WEI HE ,  QI AN XU ,  JUN JUN YU ,  HAN HAO

IPC: H01L27/08 ,  H01L23/552 ,  H01L27/088

CPC classification number: H01L27/08 ,  H01L27/0248 ,  H01L27/088 ,  Y10S257/91

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second pads to protect an internal circuit therebetween. Under a normal operating condition, a voltage on the first pad is higher than that on the second pad. The ESD protection circuit includes a substrate of a first conductivity type; first well of a second conductivity type in the substrate, wherein the first well is coupled to the first pad; a snapback device housed in the first well; and a diode string in the substrate, connected in series with the snapback device and separated from the first well, wherein the serially connected diode string and snapback device is connected between the first pad and the second pad. With the isolation from the first well, the holding voltage of the ESD protection circuit can be tuned by adjusting the number of diodes in the diode string without using a guard ring.

Abstract translation: 静电放电（ESD）保护电路耦合在第一和第二焊盘之间以保护它们之间的内部电路。 在正常工作条件下，第一焊盘上的电压高于第二焊盘上的电压。 ESD保护电路包括第一导电类型的衬底; 在衬底中的第二导电类型的第一阱，其中第一阱耦合到第一焊盘; 容纳在第一井中的快速恢复装置; 以及在所述基板中的二极管串，其与所述快速恢复装置串联连接并且与所述第一阱分离，其中所述串联连接的二极管串和快速恢复装置连接在所述第一焊盘和所述第二焊盘之间。 通过与第一个阱的隔离，ESD保护电路的保持电压可以通过调节二极管串中的二极管的数量而不使用保护环来调节。

公开(公告)号：US20130140703A1

公开(公告)日：2013-06-06

申请号：US13751486

申请日：2013-01-28

Applicant: ROUND ROCK RESEARCH, LLC

Inventor： Steven T. Harshfield

IPC: H01L29/45

CPC classification number: H01L29/45 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1691 ,  Y10S257/91

Abstract: Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

Abstract translation: 描述了环状，线性和点接触结构，其显示出比常规圆形接触插塞大大降低由光刻和沉积变化引起的对工艺偏差的敏感性。 在一个实施例中，使用诸如碳或氮化钛的标准导电材料来形成接触。 在替代实施例中，存储材料本身用于形成接触。 这些接触结构可以通过各种方法制造，包括化学机械平面化和小面刻蚀。

公开(公告)号：US20110234289A1

公开(公告)日：2011-09-29

申请号：US13047627

申请日：2011-03-14

Applicant: Vivek Subramanian ,  Patrick Smith

Inventor： Vivek Subramanian ,  Patrick Smith

IPC: H03K5/08 ,  H01L21/328 ,  H01L29/747 ,  G06K19/077

CPC classification number: H01L29/86 ,  H01L27/1285 ,  H01L27/1288 ,  H01L27/1292 ,  Y10S257/91 ,  Y10T307/964

Abstract: Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (Vt) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the Vt of an NMOS TFT (Vtn) and the Vt of a PMOS TFT (Vtp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.

Abstract translation: 公开了包含这种二极管和TFT的工艺变容二极管和二极管连接的薄膜晶体管（TFT），印刷或图案化结构（例如电路），其制造方法及其用于识别标签和传感器的应用。 包括串联的互补二极管或二极管连接的TFT的图案化结构可以稳定使用印刷或激光写入技术制造的二极管的阈值电压（Vt）。 本发明有利地利用NMOS TFT（Vtn）的Vt和PMOS TFT（Vtp）的Vt之间的间隔来建立和/或提高印刷或激光写入的二极管上的正向压降的稳定性。 本发明的其它应用涉及参考电压发生器，电压钳位电路，控制相关或差分信号传输线上的电压的方法，以及RFID和EAS标签和传感器。

公开(公告)号：US20110201200A1

公开(公告)日：2011-08-18

申请号：US13094642

申请日：2011-04-26

Applicant: Gurtej S. Sandhu ,  Bhaskar Srinivasan

Inventor： Gurtej S. Sandhu ,  Bhaskar Srinivasan

IPC: H01L23/48 ,  H01L21/28

CPC classification number: H01L45/00 ,  Y10S257/91 ,  Y10S438/90 ,  Y10S438/902 ,  Y10S438/983

Abstract: Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes.

Abstract translation: 一些实施例包括形成二极管的方法。 所述方法可以包括氧化导电电极的上表面以在导电电极上形成氧化物层。 在一些实施方案中，所述方法可包括在导电电​​极上形成可氧化材料，以及随后氧化可氧化材料以在导电电极上形成氧化物层。 在一些实施例中，所述方法可包括在导电电​​极上形成金属卤化物层。 一些实施例包括在一对二极管电极之间包含金属卤化物层的二极管。

公开(公告)号：US07951619B2

公开(公告)日：2011-05-31

申请号：US12875007

申请日：2010-09-02

Applicant: Gurtej S. Sandhu ,  Bhaskar Srinivasan

Inventor： Gurtej S. Sandhu ,  Bhaskar Srinivasan

IPC: H01L21/00

CPC classification number: H01L45/00 ,  Y10S257/91 ,  Y10S438/90 ,  Y10S438/902 ,  Y10S438/983

Abstract: Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes.

Abstract translation: 一些实施例包括形成二极管的方法。 所述方法可以包括氧化导电电极的上表面以在导电电极上形成氧化物层。 在一些实施方案中，所述方法可包括在导电电​​极上形成可氧化材料，以及随后氧化可氧化材料以在导电电极上形成氧化物层。 在一些实施例中，所述方法可包括在导电电​​极上形成金属卤化物层。 一些实施例包括在一对二极管电极之间包含金属卤化物层的二极管。

公开(公告)号：US07511352B2

公开(公告)日：2009-03-31

申请号：US10440882

申请日：2003-05-19

Applicant: Michael A. Vyvoda

Inventor： Michael A. Vyvoda

IPC: H01L27/095 ,  H01L27/112

CPC classification number: H01L23/5252 ,  H01L27/1021 ,  H01L2924/0002 ,  Y10S257/91 ,  H01L2924/00

Abstract: A monolithic three dimensional memory array comprising Schottky diodes components separated by antifuses is disclosed. The Schottky diodes are vertically oriented and disposed on alternating levels. Those on odd levels are “rightside-up” with antifuse over the metal, and those on even levels are “upside down” with metal over the antifuse. Both antifuses are preferably grown oxides.

Abstract translation: 公开了包括由反熔丝分离的肖特基二极管部件的单片三维存储器阵列。 肖特基二极管是垂直取向的并且设置在交替的电平上。 那些在奇怪的层面上是金属上的反熔丝是“右起”的，而平均层次上的那些是反金属的“颠倒”的。 两种反熔点优选是生长的氧化物。

公开(公告)号：US07511297B2

公开(公告)日：2009-03-31

申请号：US11855952

申请日：2007-09-14

Applicant: Jae-Hoon Jang ,  Ki-Nam Kim ,  Soon-Moon Jung

Inventor： Jae-Hoon Jang ,  Ki-Nam Kim ,  Soon-Moon Jung

IPC: H01L29/08 ,  H01L21/00

CPC classification number: G11C13/0004 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675 ,  H01L45/1683 ,  Y10S257/91

Abstract: A phase change memory device and a method of fabricating the same are disclosed. The phase change memory device includes a first conductor pattern having a first conductivity type and a sidewall. A second conductor pattern is connected to the sidewall of the first conductor pattern to form a diode. A phase change layer is electrically connected to the second conductor pattern and a top electrode is connected to the phase change layer.

Abstract translation: 公开了一种相变存储器件及其制造方法。 相变存储器件包括具有第一导电类型和侧壁的第一导体图案。 第二导体图案连接到第一导体图案的侧壁以形成二极管。 相变层电连接到第二导体图案，顶电极连接到相变层。

公开(公告)号：US20080206946A1

公开(公告)日：2008-08-28

申请号：US12149137

申请日：2008-04-28

Applicant: Kouichi Yamada

Inventor： Kouichi Yamada

IPC: H01L21/336

CPC classification number: H01L27/11253 ,  G11C11/15 ,  G11C17/06 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11213 ,  H01L27/11293 ,  H01L27/224 ,  Y10S257/903 ,  Y10S257/905 ,  Y10S257/909 ,  Y10S257/91

Abstract: A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode.

Abstract translation: 提供了能够减小存储单元大小的存储器。 该存储器包括形成在半导体衬底的主表面的存储单元阵列区域上的第一导电型第一杂质区，用作用于存储单元中包含的二极管的第一电极和多个第二导电型第二杂质区， 以规定的间隔形成在第一杂质区域的表面上，各自用作二极管的第二电极。

公开(公告)号：US20080032480A1

公开(公告)日：2008-02-07

申请号：US11869012

申请日：2007-10-09

Applicant: Fernando Gonzalez ,  Tyler Lowrey ,  Trung Doan ,  Raymond Turi ,  Graham Wolstenholme

Inventor： Fernando Gonzalez ,  Tyler Lowrey ,  Trung Doan ,  Raymond Turi ,  Graham Wolstenholme

IPC: H01L21/20 ,  H01L29/00

CPC classification number: H01L21/02667 ,  H01L21/02532 ,  H01L21/2022 ,  H01L27/0814 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/861 ,  H01L45/04 ,  H01L45/145 ,  Y10S257/903 ,  Y10S257/91 ,  Y10S438/979

Abstract: Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract translation: 提供了制造垂直二极管结构的半导体结构和方法。 垂直二极管结构可以具有延伸穿过绝缘层并接触硅晶片上的有源区的二极管开口。 硅化钛层可以形成在二极管开口的内表面上并与活性区接触。 二极管开口最初可以填充非晶硅插塞，其在沉积期间被掺杂并随后重结晶以形成大晶粒多晶硅。 硅插头具有可以重掺杂第一类型掺杂剂的顶部部分和可以轻掺杂第二类型掺杂剂的底部部分。 顶部可以由底部限定，以便不与硅化钛层接触。 在垂直二极管结构的一个实施例中，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

公开(公告)号：US20080017953A9

公开(公告)日：2008-01-24

申请号：US10334999

申请日：2002-12-31

Applicant: Steven Harshfield

Inventor： Steven Harshfield

IPC: H01L29/06

CPC classification number: H01L29/45 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1691 ,  Y10S257/91

Abstract: Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

Abstract translation: 描述了环状，线性和点接触结构，其显示出比常规圆形接触插塞大大降低由光刻和沉积变化引起的对工艺偏差的敏感性。 在一个实施例中，使用诸如碳或氮化钛的标准导电材料来形成接触。 在替代实施例中，存储材料本身用于形成接触。 这些接触结构可以通过各种方法制造，包括化学机械平面化和小面刻蚀。