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公开(公告)号：US10566417B2
公开(公告)日：2020-02-18
申请号：US16005782
申请日：2018-06-12
IPC分类号： H01L21/38 , H01L21/34 , H01L21/02 , H01L21/311 , H01L21/321 , H01L29/06 , H01L29/78 , H01L29/66
摘要： A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.
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公开(公告)号：US20180286866A1
公开(公告)日：2018-10-04
申请号：US15995800
申请日：2018-06-01
发明人： Kevin K. Chan , Sivananda K. Kanakasabapathy , Babar A. Khan , Masaharu Kobayashi , Effendi Leobandung , Theodorus E. Standaert , Xinhui Wang
IPC分类号： H01L27/108 , H01L29/51 , H01L29/06 , H01L29/04 , H01L49/02 , H01L27/12 , G06F17/50 , H01L21/84
CPC分类号： H01L27/10832 , G06F17/5045 , G06F17/5068 , G06F17/5072 , H01L21/84 , H01L21/845 , H01L27/0629 , H01L27/0733 , H01L27/10826 , H01L27/10829 , H01L27/10858 , H01L27/10867 , H01L27/10879 , H01L27/1203 , H01L27/1211 , H01L28/40 , H01L29/04 , H01L29/0649 , H01L29/517 , H01L29/66181 , H01L29/945
摘要： An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
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公开(公告)号：US10042968B2
公开(公告)日：2018-08-07
申请号：US15285520
申请日：2016-10-05
发明人： Kevin K. Chan , Sivananda K. Kanakasabapathy , Babar A. Khan , Masaharu Kobayashi , Effendi Leobandung , Theodorus E. Standaert , Xinhui Wang
IPC分类号： H01L27/108 , H01L21/28 , H01L29/78 , G06F17/50 , H01L21/84 , H01L29/66 , H01L29/94 , H01L27/12 , H01L49/02 , H01L29/04 , H01L27/07 , H01L27/06
摘要： An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
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公开(公告)号：US09773865B2
公开(公告)日：2017-09-26
申请号：US14492123
申请日：2014-09-22
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L21/365 , H01L21/311 , H01L21/321
CPC分类号： H01L29/0649 , H01L21/0262 , H01L21/31111 , H01L21/32105 , H01L21/34 , H01L21/38 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.
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公开(公告)号：US09711416B2
公开(公告)日：2017-07-18
申请号：US15207012
申请日：2016-07-11
发明人： Kevin K. Chan , Young-Hee Kim , Masaharu Kobayashi , Jinghong Li , Dae-Gyu Park
IPC分类号： H01L29/66 , H01L21/84 , H01L29/78 , H01L29/10 , H01L27/12 , H01L21/02 , H01L21/16 , H01L21/265 , H01L29/06
CPC分类号： H01L21/845 , H01L21/02524 , H01L21/02529 , H01L21/02532 , H01L21/02598 , H01L21/02636 , H01L21/165 , H01L21/26513 , H01L27/1211 , H01L29/0649 , H01L29/1054 , H01L29/66795 , H01L29/7849 , H01L29/785
摘要： A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.
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公开(公告)号：US09679775B2
公开(公告)日：2017-06-13
申请号：US15211010
申请日：2016-07-15
发明人： Kevin K. Chan , Marinus J. P. Hopstaken , Young-Hee Kim , Masaharu Kobayashi , Effendi Leobandung , Deborah A. Neumayer , Dae-Gyu Park , Uzma Rana , Tsong-Lin Tai
IPC分类号： H01L21/225 , H01L29/66 , H01L21/24 , H01L29/45 , H01L21/285 , H01L21/322 , H01L21/324 , H01L29/267 , H01L29/51
CPC分类号： H01L21/242 , H01L21/2257 , H01L21/2258 , H01L21/28575 , H01L21/3228 , H01L21/3245 , H01L29/267 , H01L29/452 , H01L29/517 , H01L29/665 , H01L29/66522 , H01L29/66742 , H01L29/78618 , H01L29/78681
摘要： An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.
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公开(公告)号：US20160322500A1
公开(公告)日：2016-11-03
申请号：US15207012
申请日：2016-07-11
发明人： Kevin K. Chan , Young-Hee Kim , Masaharu Kobayashi , Jinghong Li , Dae-Gyu Park
CPC分类号： H01L21/845 , H01L21/02524 , H01L21/02529 , H01L21/02532 , H01L21/02598 , H01L21/02636 , H01L21/165 , H01L21/26513 , H01L27/1211 , H01L29/0649 , H01L29/1054 , H01L29/66795 , H01L29/7849 , H01L29/785
摘要： A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.
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公开(公告)号：US09418846B1
公开(公告)日：2016-08-16
申请号：US14634050
申请日：2015-02-27
发明人： Kevin K. Chan , Marinus J. P. Hopstaken , Young-Hee Kim , Masaharu Kobayashi , Effendi Leobandung , Deborah A. Neumayer , Dae-Gyu Park , Uzma Rana , Tsong-Lin Tai
IPC分类号： H01L21/02 , H01L29/207 , H01L21/225
CPC分类号： H01L21/242 , H01L21/2257 , H01L21/2258 , H01L21/28575 , H01L21/3228 , H01L21/3245 , H01L29/267 , H01L29/452 , H01L29/517 , H01L29/665 , H01L29/66522 , H01L29/66742 , H01L29/78618 , H01L29/78681
摘要： An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Additionally, the approach includes performing a low temperature anneal in an oxygen free environment followed by depositing a metal layer on the dopant layer. Furthermore, the approach includes alloying the metal layer with the dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.
摘要翻译： 提供在半导体器件中形成掺杂剂结的方法的方法。 该方法包括对半导体层的暴露表面进行表面改性处理，并在半导体层的暴露表面上沉积掺杂剂材料。 另外，该方法包括在无氧环境中进行低温退火，然后在掺杂剂层上沉积金属层。 此外，该方法包括将金属层与掺杂剂层合金化以形成半导体器件结，其中半导体层由III-V族半导体材料组成，表面改性处理发生在真空室中以从暴露的表面去除表面氧化物 半导体层的表面，并且上述每个过程在低温下发生。
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9.发明授权Process variability tolerant hard mask for replacement metal gate finFET devices 有权用于更换金属栅极finFET器件的工艺变异性容忍硬掩模公开(公告)号：US09034748B2
公开(公告)日：2015-05-19
申请号：US14017918
申请日：2013-09-04
发明人： Christopher V. Baiocco , Kevin K. Chan , Young-Hee Kim , Masaharu Kobayashi , Effendi Leobandung , Fei Liu , Dae-Gyu Park , Helen Wang , Xinhui Wang , Min Yang
IPC分类号： H01L21/302 , H01L21/461 , H01L21/28 , H01L29/66 , H01L21/033 , H01L21/3213
CPC分类号： H01L21/28132 , H01L21/0332 , H01L21/31055 , H01L21/31116 , H01L21/31144 , H01L21/32139 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L29/66545 , H01L29/6681 , Y10S438/95
摘要： Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.
摘要翻译： 实施例包括一种方法，包括在第一层上沉积硬掩模层，硬掩模层包括： 下硬掩模层，硬掩模停止层和上硬掩模。 图案化硬掩模层和第一层，并且沉积在图案化侧壁上的间隔物。 通过相对于硬掩模阻挡层的选择性蚀刻去除上部硬掩模层和间隔物的顶部，剩余的间隔物材料延伸到侧壁上的第一预定位置。 通过相对于下部硬掩模层和间隔物的选择性蚀刻除去硬掩模阻挡层。 通过相对于第一层选择性地蚀刻下部硬掩模层和间隔物来去除间隔物的第一硬掩模层和顶部，剩余的间隔物材料延伸到侧壁上的第二预定位置。
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10.发明申请公开(公告)号：US20140332851A1
公开(公告)日：2014-11-13
申请号：US14027609
申请日：2013-09-16
发明人： Cheng-Wei Cheng , Shu-Jen Han , Masaharu Kobayashi , Ko-Tao Lee , Devendra K. Sadana , Kuen-Ting Shiu
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L23/485 , H01L29/0847 , H01L29/1083 , H01L29/20 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/517 , H01L29/66522 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/7838 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region.
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