知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

49 条记录 (耗时 0.022 秒)

    SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE
    3.
    发明申请
    SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE 审中-公开
    具有深度电容电容器的半导体结构及其制造方法

    公开(公告)号：US20150135156A1

    公开(公告)日：2015-05-14

    申请号：US14601288

    申请日：2015-01-21

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Kevin K. Chan ,  Sivananda K. Kanakasabapathy ,  Babar A. Khan ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Theodorus E. Standaert ,  Xinhui Wang

    IPC分类号： G06F17/50

    摘要： An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

    摘要翻译： 公开了一种集成的FinFET和深沟槽电容器结构及其制造方法。 该方法包括在绝缘体上硅（SOI）衬底上形成至少一个深沟槽电容器。 该方法还包括从SOI衬底同时从至少一个深沟槽电容器的材料和SOI散热片形成多晶硅鳍片。 该方法还包括在多晶硅鳍片上形成绝缘体层。 该方法还包括在多晶硅鳍片上的SOI散热片和绝缘体层上形成栅极结构。

    PROCESS VARIABILITY TOLERANT HARD MASK FOR REPLACEMENT METAL GATE FINFET DEVICES
    4.
    发明申请
    PROCESS VARIABILITY TOLERANT HARD MASK FOR REPLACEMENT METAL GATE FINFET DEVICES 有权
    过程变异耐用硬掩模用于更换金属栅极FINFET器件

    公开(公告)号：US20150064897A1

    公开(公告)日：2015-03-05

    申请号：US14017918

    申请日：2013-09-04

    申请人： International Business Machines Corporation

    发明人： Christopher V. Baiocco ,  Kevin K. Chan ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Fei Liu ,  Dae-Gyu Park ,  Helen Wang ,  Xinhui Wang ,  Min Yang

    IPC分类号： H01L21/28 ,  H01L29/66

    CPC分类号： H01L21/28132 ,  H01L21/0332 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/6681 ,  Y10S438/95

    摘要： Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.

    摘要翻译： 实施例包括一种方法，包括在第一层上沉积硬掩模层，硬掩模层包括： 下硬掩模层，硬掩模停止层和上硬掩模。 图案化硬掩模层和第一层，并且沉积在图案化侧壁上的间隔物。 通过相对于硬掩模阻挡层的选择性蚀刻去除上部硬掩模层和间隔物的顶部，剩余的间隔物材料延伸到侧壁上的第一预定位置。 通过相对于下部硬掩模层和间隔物的选择性蚀刻除去硬掩模阻挡层。 通过相对于第一层选择性地蚀刻下部硬掩模层和间隔物来去除间隔物的第一硬掩模层和顶部，剩余的间隔物材料延伸到侧壁上的第二预定位置。

    Uniform finFET gate height
    6.
    发明授权
    Uniform finFET gate height 有权
    均匀finFET栅极高度

    公开(公告)号：US08928057B2

    公开(公告)日：2015-01-06

    申请号：US13689924

    申请日：2012-11-30

    申请人： International Business Machines Corporation

    发明人： William Cote ,  Johnathan E. Faltermeier ,  Babar A. Khan ,  Ravikumar Ramachandran ,  Theodorus E. Standaert ,  Xinhui Wang

    IPC分类号： H01L29/94 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12

    CPC分类号： H01L29/945 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66181 ,  H01L29/66545

    摘要： A method including providing fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the fins and the nitride layer, removing a portion of the fins to form an opening, forming a dielectric spacer on a sidewall of the opening, and filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer. The method may further include forming a deep trench capacitor in-line with one of the fins, removing the nitride layer to form a gap between the fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the fins and the fill material to widen.

    摘要翻译： 一种方法，包括提供从半导体衬底蚀刻并被氧化物层和氮化物层覆盖的散热片，所述氧化物层位于所述散热片和所述氮化物层之间，去除所述翅片的一部分以形成开口，形成介电隔离物 开口的侧壁，并用填充材料填充开口，其中填充材料的顶表面基本上与氮化物层的顶表面齐平。 该方法还可以包括形成与其中一个鳍片成直角的深沟槽电容器，去除氮化物层以在散热片和填充材料之间形成间隙，其中填充材料具有在间隙上延伸的重新排列的几何形状，以及 去除重入的几何形状并使翅片和填充材料之间的间隙变宽。

    Method of Manufacturing a Thin Box Metal Backgate Extremely Thin SOI Device
    7.
    发明申请
    Method of Manufacturing a Thin Box Metal Backgate Extremely Thin SOI Device 有权
    薄盒金属背栅非常薄的SOI器件的制造方法

    公开(公告)号：US20130122665A1

    公开(公告)日：2013-05-16

    申请号：US13736994

    申请日：2013-01-09

    申请人： International Business Machines Corporation

    发明人： Kevin K. Chan ,  Zhibin Ren ,  Xinhui Wang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7827 ,  H01L21/7624 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78696

    摘要： SOI structures with silicon layers less than 20 nm thick are used to form ETSOI semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate encapsulated by thin nitride layers to prevent metal oxidation, the tungsten backgate being characterized by its low resistivity. The structure includes at least one FET having a gate stack formed by a high-K metal gate and a tungsten region superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer as a channel. The SOI structure thus formed controls the Vt variation from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and lowers the drain induced bias and sub-threshold swings. The structure supports the evidence of the stability of the wafer having a tungsten film during thermal processing, during STI and contact formation.

    摘要翻译： 使用硅层小于20nm厚的SOI结构来形成ETSOI半导体器件。 ETSOI器件使用由薄氮化物层封装的薄钨背栅来制造，以防止金属氧化，钨背栅的特征在于其低电阻率。 该结构包括至少一个FET，其具有由高K金属栅极和叠加在其上的钨区域形成的栅极堆叠，栅极堆叠的覆盖区域利用薄SOI层作为沟道。 这样形成的SOI结构控制了薄SOI厚度和其中的掺杂剂的Vt变化。 ETSOI高K金属背栅完全耗尽器件与薄BOX结合提供了出色的短通道控制，并降低了漏极引起的偏置和次阈值摆幅。 该结构支持在STI和接触形成期间在热处理期间具有钨膜的晶片的稳定性的证据。