公开(公告)号：US20150064897A1

公开(公告)日：2015-03-05

申请号：US14017918

申请日：2013-09-04

申请人： International Business Machines Corporation

发明人： Christopher V. Baiocco ,  Kevin K. Chan ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Fei Liu ,  Dae-Gyu Park ,  Helen Wang ,  Xinhui Wang ,  Min Yang

IPC分类号： H01L21/28 ,  H01L29/66

CPC分类号： H01L21/28132 ,  H01L21/0332 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/6681 ,  Y10S438/95

摘要： Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.

摘要翻译： 实施例包括一种方法，包括在第一层上沉积硬掩模层，硬掩模层包括： 下硬掩模层，硬掩模停止层和上硬掩模。 图案化硬掩模层和第一层，并且沉积在图案化侧壁上的间隔物。 通过相对于硬掩模阻挡层的选择性蚀刻去除上部硬掩模层和间隔物的顶部，剩余的间隔物材料延伸到侧壁上的第一预定位置。 通过相对于下部硬掩模层和间隔物的选择性蚀刻除去硬掩模阻挡层。 通过相对于第一层选择性地蚀刻下部硬掩模层和间隔物来去除间隔物的第一硬掩模层和顶部，剩余的间隔物材料延伸到侧壁上的第二预定位置。

公开(公告)号：US20150287629A1

公开(公告)日：2015-10-08

申请号：US14741618

申请日：2015-06-17

申请人： International Business Machines Corporation

发明人： Christopher V. Baiocco ,  Michael P. Chudzik ,  Deleep R. Nair ,  Jay M. Shah

IPC分类号： H01L21/762 ,  H01L29/06

CPC分类号： H01L21/76224 ,  H01L21/762 ,  H01L29/0649 ,  H01L29/66537 ,  H01L29/783

摘要： Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.

摘要翻译： 嵌入隔离结构中的氧气清除材料提供了从氧污染中改进的高介电常数（Hi-K）材料的保护，同时避免了包括这种Hi-K材料在内的晶体管的功函数和切换阈值偏移的变化。

公开(公告)号：US20130337624A1

公开(公告)日：2013-12-19

申请号：US13773881

申请日：2013-02-22

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Christopher V. Baiocco ,  Daniel J. Jaeger ,  Carl J. Radens ,  Helen Wang

IPC分类号： H01L29/66

CPC分类号： H01L29/7816 ,  H01L21/28247 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/78

摘要： A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.

公开(公告)号：US20130140670A1

公开(公告)日：2013-06-06

申请号：US13759429

申请日：2013-02-05

申请人： International Business Machines Corporation

发明人： Michael V. Aquilino ,  Christopher V. Baiocco ,  Richard A. Conti ,  Daniel J. Jaeger ,  Vijay Narayanan

IPC分类号： H01L29/06

CPC分类号： H01L29/0649 ,  H01L21/76229 ,  H01L29/517

摘要： A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.

摘要翻译： 提供基板。 在衬底中形成STI沟槽。 填充材料形成在STI沟槽中，然后平坦化。 将衬底暴露于氧化环境中，在STI沟槽的底部和侧壁处生长衬垫。 衬垫降低了高k金属栅极器件中的Vt-W效应。

公开(公告)号：US09034748B2

公开(公告)日：2015-05-19

申请号：US14017918

申请日：2013-09-04

申请人： International Business Machines Corporation

发明人： Christopher V. Baiocco ,  Kevin K. Chan ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Fei Liu ,  Dae-Gyu Park ,  Helen Wang ,  Xinhui Wang ,  Min Yang

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/28 ,  H01L29/66 ,  H01L21/033 ,  H01L21/3213

CPC分类号： H01L21/28132 ,  H01L21/0332 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/6681 ,  Y10S438/95

摘要： Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.

摘要翻译： 实施例包括一种方法，包括在第一层上沉积硬掩模层，硬掩模层包括： 下硬掩模层，硬掩模停止层和上硬掩模。 图案化硬掩模层和第一层，并且沉积在图案化侧壁上的间隔物。 通过相对于硬掩模阻挡层的选择性蚀刻去除上部硬掩模层和间隔物的顶部，剩余的间隔物材料延伸到侧壁上的第一预定位置。 通过相对于下部硬掩模层和间隔物的选择性蚀刻除去硬掩模阻挡层。 通过相对于第一层选择性地蚀刻下部硬掩模层和间隔物来去除间隔物的第一硬掩模层和顶部，剩余的间隔物材料延伸到侧壁上的第二预定位置。

公开(公告)号：US08629028B2

公开(公告)日：2014-01-14

申请号：US13773881

申请日：2013-02-22

申请人： International Business Machines Corporation

发明人： Christopher V. Baiocco ,  Daniel J. Jaeger ,  Carl J. Radens ,  Helen Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/7816 ,  H01L21/28247 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/78

摘要： A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.