公开(公告)号：US09711416B2

公开(公告)日：2017-07-18

申请号：US15207012

申请日：2016-07-11

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Jinghong Li ,  Dae-Gyu Park

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/78 ,  H01L29/10 ,  H01L27/12 ,  H01L21/02 ,  H01L21/16 ,  H01L21/265 ,  H01L29/06

CPC classification number: H01L21/845 ,  H01L21/02524 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/02636 ,  H01L21/165 ,  H01L21/26513 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.

公开(公告)号：US09679775B2

公开(公告)日：2017-06-13

申请号：US15211010

申请日：2016-07-15

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Marinus J. P. Hopstaken ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Deborah A. Neumayer ,  Dae-Gyu Park ,  Uzma Rana ,  Tsong-Lin Tai

IPC: H01L21/225 ,  H01L29/66 ,  H01L21/24 ,  H01L29/45 ,  H01L21/285 ,  H01L21/322 ,  H01L21/324 ,  H01L29/267 ,  H01L29/51

CPC classification number: H01L21/242 ,  H01L21/2257 ,  H01L21/2258 ,  H01L21/28575 ,  H01L21/3228 ,  H01L21/3245 ,  H01L29/267 ,  H01L29/452 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78681

Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

公开(公告)号：US20160322500A1

公开(公告)日：2016-11-03

申请号：US15207012

申请日：2016-07-11

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Jinghong Li ,  Dae-Gyu Park

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/02524 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/02636 ,  H01L21/165 ,  H01L21/26513 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.

公开(公告)号：US09418846B1

公开(公告)日：2016-08-16

申请号：US14634050

申请日：2015-02-27

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Marinus J. P. Hopstaken ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Deborah A. Neumayer ,  Dae-Gyu Park ,  Uzma Rana ,  Tsong-Lin Tai

IPC: H01L21/02 ,  H01L29/207 ,  H01L21/225

CPC classification number: H01L21/242 ,  H01L21/2257 ,  H01L21/2258 ,  H01L21/28575 ,  H01L21/3228 ,  H01L21/3245 ,  H01L29/267 ,  H01L29/452 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78681

Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Additionally, the approach includes performing a low temperature anneal in an oxygen free environment followed by depositing a metal layer on the dopant layer. Furthermore, the approach includes alloying the metal layer with the dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

Abstract translation: 提供在半导体器件中形成掺杂剂结的方法的方法。 该方法包括对半导体层的暴露表面进行表面改性处理，并在半导体层的暴露表面上沉积掺杂剂材料。 另外，该方法包括在无氧环境中进行低温退火，然后在掺杂剂层上沉积金属层。 此外，该方法包括将金属层与掺杂剂层合金化以形成半导体器件结，其中半导体层由III-V族半导体材料组成，表面改性处理发生在真空室中以从暴露的表面去除表面氧化物 半导体层的表面，并且上述每个过程在低温下发生。

公开(公告)号：US09397161B1

公开(公告)日：2016-07-19

申请号：US14631886

申请日：2015-02-26

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Pranita Kerber ,  Young-Hee Kim ,  Effendi Leobandung ,  Yanning Sun

IPC: H01L21/205 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L29/36 ,  H01L29/38 ,  H01L21/18 ,  H01L21/20

CPC classification number: H01L29/20 ,  H01L21/02392 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0257 ,  H01L21/30612 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/8252 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/12 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.

Abstract translation: 一种用于制造半导体器件的方法可以包括：接收包括衬底的门控衬底，沟道层和形成在其上的栅极结构，在衬底上过蚀刻沟道层以露出栅极结构下方的延伸区域，在 暴露的延伸区域使用第一原位掺杂剂并且使用第二原位掺杂剂在卤素层上外延生长源极或漏极，其中第一原位掺杂剂和第二原位掺杂剂具有相反的掺杂极性。 使用相反的掺杂极性可以为半导体器件提供能带屏障并减少漏电流。 本文还公开了相应的装置。

公开(公告)号：US09034748B2

公开(公告)日：2015-05-19

申请号：US14017918

申请日：2013-09-04

Applicant: International Business Machines Corporation

Inventor： Christopher V. Baiocco ,  Kevin K. Chan ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Fei Liu ,  Dae-Gyu Park ,  Helen Wang ,  Xinhui Wang ,  Min Yang

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/28 ,  H01L29/66 ,  H01L21/033 ,  H01L21/3213

CPC classification number: H01L21/28132 ,  H01L21/0332 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/6681 ,  Y10S438/95

Abstract: Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.

Abstract translation: 实施例包括一种方法，包括在第一层上沉积硬掩模层，硬掩模层包括： 下硬掩模层，硬掩模停止层和上硬掩模。 图案化硬掩模层和第一层，并且沉积在图案化侧壁上的间隔物。 通过相对于硬掩模阻挡层的选择性蚀刻去除上部硬掩模层和间隔物的顶部，剩余的间隔物材料延伸到侧壁上的第一预定位置。 通过相对于下部硬掩模层和间隔物的选择性蚀刻除去硬掩模阻挡层。 通过相对于第一层选择性地蚀刻下部硬掩模层和间隔物来去除间隔物的第一硬掩模层和顶部，剩余的间隔物材料延伸到侧壁上的第二预定位置。

公开(公告)号：US20160329211A1

公开(公告)日：2016-11-10

申请号：US15211010

申请日：2016-07-15

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Marinus J.P. Hopstaken ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Deborah A. Neumayer ,  Dae-Gyu Park ,  Uzma Rana ,  Tsong-Lin Tai

IPC: H01L21/24 ,  H01L29/66 ,  H01L21/225 ,  H01L29/267 ,  H01L21/322 ,  H01L21/324

CPC classification number: H01L21/242 ,  H01L21/2257 ,  H01L21/2258 ,  H01L21/28575 ,  H01L21/3228 ,  H01L21/3245 ,  H01L29/267 ,  H01L29/452 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78681

Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

Abstract translation: 提供在半导体器件中形成掺杂剂结的方法的方法。 该方法包括对半导体层的暴露表面进行表面改性处理，并在半导体层的暴露表面上沉积掺杂剂材料。 此外，该方法包括使金属层与掺杂剂层合金以形成半导体器件结，其中半导体层由III-V族半导体材料组成，表面改性处理发生在真空室中以从暴露的表面去除表面氧化物 半导体层的表面，并且上述每个过程在低温下发生。

公开(公告)号：US20150064897A1

公开(公告)日：2015-03-05

申请号：US14017918

申请日：2013-09-04

Applicant: International Business Machines Corporation

Inventor： Christopher V. Baiocco ,  Kevin K. Chan ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Fei Liu ,  Dae-Gyu Park ,  Helen Wang ,  Xinhui Wang ,  Min Yang

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28132 ,  H01L21/0332 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/6681 ,  Y10S438/95

Abstract: Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.

Abstract translation: 实施例包括一种方法，包括在第一层上沉积硬掩模层，硬掩模层包括： 下硬掩模层，硬掩模停止层和上硬掩模。 图案化硬掩模层和第一层，并且沉积在图案化侧壁上的间隔物。 通过相对于硬掩模阻挡层的选择性蚀刻去除上部硬掩模层和间隔物的顶部，剩余的间隔物材料延伸到侧壁上的第一预定位置。 通过相对于下部硬掩模层和间隔物的选择性蚀刻除去硬掩模阻挡层。 通过相对于第一层选择性地蚀刻下部硬掩模层和间隔物来去除间隔物的第一硬掩模层和顶部，剩余的间隔物材料延伸到侧壁上的第二预定位置。

公开(公告)号：US20140148003A1

公开(公告)日：2014-05-29

申请号：US13684869

申请日：2012-11-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Effendi Leobandung ,  William Cote ,  Laertis Economikos ,  Young-Hee Kim ,  Dae-Gyu Park ,  Theodorus Eduardus Standaert ,  Kenneth Jay Stein ,  YS Suh ,  Min Yang

IPC: H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28008 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: Methods of fabricating replacement metal gate transistors using bi-layer a hardmask are disclosed. By utilizing a bi-layer hardmask comprised of a first layer of nitride, followed by a second layer of oxide, the topography issues caused by transition regions of gates are mitigated, which simplifies downstream processing steps and improves yield.

Abstract translation: 公开了使用双层硬掩模制造替代金属栅极晶体管的方法。 通过利用由第一层氮化物构成的双层硬掩模，随后是第二层氧化物，减轻了由栅极的过渡区域引起的形貌问题，这简化了下游处理步骤并提高了产量。

公开(公告)号：US20160254352A1

公开(公告)日：2016-09-01

申请号：US15146148

申请日：2016-05-04

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Pranita Kerber ,  Young-Hee Kim ,  Effendi Leobandung ,  Yanning Sun

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L29/207 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L29/20 ,  H01L21/02392 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0257 ,  H01L21/30612 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/8252 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/12 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.