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公开(公告)号：US20200381624A1
公开(公告)日：2020-12-03
申请号：US16428554
申请日：2019-05-31
Inventor： Steven Consiglio , Cory Wajda , Kandabara Tapily , Takaaki Tsunomura , Takashi Ando , Paul C. Jamison , Eduard A. Cartier , Vijay Narayanan , Marinus J.P. Hopstaken
Abstract: A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing H2 gas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.
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公开(公告)号：US20160329211A1
公开(公告)日：2016-11-10
申请号：US15211010
申请日：2016-07-15
Applicant: International Business Machines Corporation
Inventor： Kevin K. Chan , Marinus J.P. Hopstaken , Young-Hee Kim , Masaharu Kobayashi , Effendi Leobandung , Deborah A. Neumayer , Dae-Gyu Park , Uzma Rana , Tsong-Lin Tai
IPC: H01L21/24 , H01L29/66 , H01L21/225 , H01L29/267 , H01L21/322 , H01L21/324
CPC classification number: H01L21/242 , H01L21/2257 , H01L21/2258 , H01L21/28575 , H01L21/3228 , H01L21/3245 , H01L29/267 , H01L29/452 , H01L29/517 , H01L29/665 , H01L29/66522 , H01L29/66742 , H01L29/78618 , H01L29/78681
Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.
Abstract translation: 提供在半导体器件中形成掺杂剂结的方法的方法。 该方法包括对半导体层的暴露表面进行表面改性处理，并在半导体层的暴露表面上沉积掺杂剂材料。 此外，该方法包括使金属层与掺杂剂层合金以形成半导体器件结，其中半导体层由III-V族半导体材料组成，表面改性处理发生在真空室中以从暴露的表面去除表面氧化物 半导体层的表面，并且上述每个过程在低温下发生。
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Patent Agency Ranking
公开(公告)号：US20210234096A1
公开(公告)日：2021-07-29
申请号：US17226495
申请日：2021-04-09
Inventor： Steven Consiglio , Cory Wajda , Kandabara Tapily , Takaaki Tsunomura , Takashi Ando , Paul C. Jamison , Eduard A. Cartier , Vijay Narayanan , Marinus J.P. Hopstaken
Abstract: A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing H2 gas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.
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公开(公告)号：US20180175174A1
公开(公告)日：2018-06-21
申请号：US15383537
申请日：2016-12-19
Applicant: International Business Machines Corporation
Inventor： John Bruley , Marinus J.P. Hopstaken , Kam-Leung Lee
IPC: H01L29/66 , H01L21/265 , H01L29/10 , H01L29/207
CPC classification number: H01L29/66803 , H01L21/26546 , H01L21/26586 , H01L29/1041 , H01L29/207
Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a shallow, abrupt and highly activated tin (Sn) extension implant junction. The method includes forming a semiconductor fin on a substrate. A gate is formed over a channel region of the semiconductor fin. A Sn extension implant junction is formed on a surface of the semiconductor fin in the channel region.
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公开(公告)号：US20170250302A1
公开(公告)日：2017-08-31
申请号：US15592669
申请日：2017-05-11
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Talia S. Gershon , Marinus J.P. Hopstaken , Jeehwan Kim , Yun Seog Lee
IPC: H01L31/065 , H01L31/18 , H01L31/0368 , H01L31/032 , H01L31/0224
CPC classification number: H01L31/065 , H01L31/022466 , H01L31/0326 , H01L31/0368 , H01L31/1864 , H01L31/1884 , Y02E10/50
Abstract: A method for fabricating a photovoltaic device includes forming a polycrystalline absorber layer including Cu—Zn—Sn—S(Se) (CZTSSe) over a substrate. The absorber layer is rapid thermal annealed in a sealed chamber having elemental sulfur within the chamber. A sulfur content profile is graded in the absorber layer in accordance with a size of the elemental sulfur and an anneal temperature to provide a graduated bandgap profile for the absorber layer. Additional layers are formed on the absorber layer to complete the photovoltaic device.
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公开(公告)号：US20170077337A1
公开(公告)日：2017-03-16
申请号：US14853463
申请日：2015-09-14
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Talia S. Gershon , Marinus J.P. Hopstaken , Jeehwan Kim , Yun Seog Lee
IPC: H01L31/065 , H01L31/0368 , H01L31/18 , H01L31/032
CPC classification number: H01L31/065 , H01L31/022466 , H01L31/0326 , H01L31/0368 , H01L31/1864 , H01L31/1884 , Y02E10/50
Abstract: A method for fabricating a photovoltaic device includes forming a polycrystalline absorber layer including Cu—Zn—Sn—S(Se) (CZTSSe) over a substrate. The absorber layer is rapid thermal annealed in a sealed chamber having elemental sulfur within the chamber. A sulfur content profile is graded in the absorber layer in accordance with a size of the elemental sulfur and an anneal temperature to provide a graduated bandgap profile for the absorber layer. Additional layers are formed on the absorber layer to complete the photovoltaic device.
Abstract translation: 制造光电器件的方法包括在衬底上形成包含Cu-Zn-Sn-S（Se）（CZTSSe）的多晶吸收体层。 吸收层在室内具有元素硫的密封室中快速热退火。 硫含量分布根据元素硫的大小和退火温度在吸收层中分级，以提供吸收层的刻度带隙分布。 在吸收层上形成附加层以完成光伏器件。
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公开(公告)号：US20160254150A1
公开(公告)日：2016-09-01
申请号：US14634050
申请日：2015-02-27
Applicant: International Business Machines Corporation
Inventor： Kevin K. Chan , Marinus J.P. Hopstaken , Young-Hee Kim , Masaharu Kobayashi , Effendi Leobandung , Deborah A. Neumayer , Dae-Gyu Park , Uzma Rana , Tsong-Lin Tai
IPC: H01L21/02 , H01L21/225 , H01L29/207
CPC classification number: H01L21/242 , H01L21/2257 , H01L21/2258 , H01L21/28575 , H01L21/3228 , H01L21/3245 , H01L29/267 , H01L29/452 , H01L29/517 , H01L29/665 , H01L29/66522 , H01L29/66742 , H01L29/78618 , H01L29/78681
Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Additionally, the approach includes performing a low temperature anneal in an oxygen free environment followed by depositing a metal layer on the dopant layer. Furthermore, the approach includes alloying the metal layer with the dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.
Abstract translation: 提供在半导体器件中形成掺杂剂结的方法的方法。 该方法包括对半导体层的暴露表面进行表面改性处理，并在半导体层的暴露表面上沉积掺杂剂材料。 此外，该方法包括在无氧环境中进行低温退火，然后在掺杂剂层上沉积金属层。 此外，该方法包括将金属层与掺杂剂层合金化以形成半导体器件结，其中半导体层由III-V族半导体材料组成，表面改性处理发生在真空室中以从暴露的表面去除表面氧化物 半导体层的表面，并且上述每个过程在低温下发生。
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