REDUCING GATE HEIGHT VARIATION IN RMG PROCESS
    9.
    发明申请
    REDUCING GATE HEIGHT VARIATION IN RMG PROCESS 审中-公开
    减少闸门高度变化在RMG过程

    公开(公告)号:US20150111373A1

    公开(公告)日:2015-04-23

    申请号:US14057357

    申请日:2013-10-18

    Abstract: A method of forming transistors is provided. The method includes forming a plurality of transistor structures to have a plurality of dummy gates on a substrate. Each dummy gate is surrounded by sidewall spacers of a height, which is less than the dummy gate and is different for different transistor structures resulting in divots of different depths above the sidewall spacers. The method then deposits a conformal dielectric layer on top of the dummy gates and inside the divots of the plurality of transistor structures with the conformal dielectric layer having a thickness of at least half of a width of the divots, removes only a portion of the conformal dielectric layer that is on top of the dummy gates to expose the dummy gates; and replaces the dummy gates with a plurality of high-k metal gates.

    Abstract translation: 提供一种形成晶体管的方法。 该方法包括形成多个晶体管结构以在衬底上具有多个虚拟栅极。 每个虚拟栅极被高度的侧壁间隔物包围,该间隙小于虚拟栅极,并且对于不同的晶体管结构是不同的,导致在侧壁间隔物上方具有不同深度的裂缝。 该方法然后在保持电介质层的厚度至少为纹理宽度的一半之上的情况下,在虚拟栅极的顶部和多个晶体管结构的纹间之内沉积保形介电层,仅去除一部分保形 位于伪栅极顶部以暴露伪栅极的介电层; 并且用多个高k金属栅极代替伪栅极。

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