公开(公告)号：US11967645B2

公开(公告)日：2024-04-23

申请号：US17390565

申请日：2021-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yogendra Yadav ,  Chi-Chih Chen ,  Ruey-Hsin Liu ,  Chih-Wen Yao

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L27/07

CPC classification number: H01L29/7823 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835 ,  H01L27/0733 ,  H01L29/0847

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a field plate, a gate electrode, and a first dielectric layer. The substrate has a top surface. The substrate includes a first drift region with a first conductivity type extending from the top surface of the substrate into the substrate, and includes a second drill region with the first conductivity type extending from the top surface of the substrate into the substrate and adjacent to the first drift region. The field plate is over the substrate. The gate electrode has a first portion and a second portion, wherein the first portion of the gate electrode is located over the field plate. The first dielectric layer is between the substrate and the field plate. The first portion of the gate electrode is overlapping with a boundary of the first drift region and the second drift region in the substrate.

公开(公告)号：US11942431B2

公开(公告)日：2024-03-26

申请号：US17874565

申请日：2022-07-27

Applicant: KIOXIA CORPORATION

Inventor： Nobuyuki Momo ,  Keisuke Nakatsuka

IPC: H01L23/538 ,  H01L23/482 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L27/07 ,  H01L27/08 ,  H01L49/02

CPC classification number: H01L23/5386 ,  H01L23/4821 ,  H01L23/5223 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0733 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/0603 ,  H01L2224/8034 ,  H01L2924/1205 ,  H01L2924/19041

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip including a first metal pad and a second metal pad; and a second semiconductor chip including a third metal pad and a fourth metal pad, the third metal pad joined to the first metal pad, the fourth metal pad coupled to the second metal pad via a dielectric layer, wherein the second semiconductor chip is coupled to the first semiconductor chip via the first metal pad and the third metal pad.

公开(公告)号：US11916100B2

公开(公告)日：2024-02-27

申请号：US17699649

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsuan-Han Tseng ,  Chun-Yuan Chen ,  Lu-Sheng Chou ,  Hsiao-Hui Tseng ,  Ching-Chun Wang

IPC: H01L29/94 ,  H01L27/07 ,  H01L49/02

CPC classification number: H01L28/75 ,  H01L27/0733 ,  H01L28/91 ,  H01L28/92 ,  H01L29/945

Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

公开(公告)号：US20230345736A1

公开(公告)日：2023-10-26

申请号：US18341793

申请日：2023-06-27

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Chenchen Jacob Wang ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui ,  Sai-Hooi Yeong

IPC: H10B53/30 ,  H01L27/07 ,  H01L27/06 ,  H01L23/522

CPC classification number: H10B53/30 ,  H01L27/0733 ,  H01L28/60 ,  H01L27/0629 ,  H01L23/5223 ,  H01L21/56

Abstract: A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad.

公开(公告)号：US20180277533A1

公开(公告)日：2018-09-27

申请号：US15991195

申请日：2018-05-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Yutaka OKAZAKI

IPC: H01L27/07 ,  H01G4/008 ,  H01G4/10 ,  H01G4/40 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L29/94 ,  H05K1/18

CPC classification number: H01L27/0733 ,  H01G4/008 ,  H01G4/105 ,  H01G4/40 ,  H01L21/8258 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/66477 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/94 ,  H05K1/18 ,  H05K2201/10015 ,  H05K2201/10083 ,  H05K2201/10166

Abstract: A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.

公开(公告)号：US09917081B2

公开(公告)日：2018-03-13

申请号：US15181676

申请日：2016-06-14

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/78 ,  H01L29/93 ,  H01L29/10

CPC classification number: H01L27/0629 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/823431 ,  H01L27/0733 ,  H01L29/1083 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/785 ,  H01L29/93

Abstract: A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.

公开(公告)号：US09853022B2

公开(公告)日：2017-12-26

申请号：US15272499

申请日：2016-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L21/8242 ,  H01L27/06 ,  H01L27/07 ,  H01L29/66 ,  H01L49/02 ,  H01L23/522 ,  H01L21/28 ,  H01L29/40 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L27/0629 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/31051 ,  H01L21/32115 ,  H01L23/5223 ,  H01L27/0733 ,  H01L28/40 ,  H01L28/60 ,  H01L28/86 ,  H01L28/88 ,  H01L29/401 ,  H01L29/66409 ,  H01L29/66545

Abstract: A method is provided for forming a metal-insulator-metal capacitor in a replacement metal gate module. The method includes providing a gate cap formed on a gate. The method further includes removing a portion of the gate cap and forming a recess in the gate. A remaining portion of the gate forms a first electrode of the capacitor. The method also includes depositing a dielectric on remaining portions of the gate cap and the remaining portion of the gate. The method additionally includes depositing a conductive material on the dielectric. The method further includes removing a portion of the conductive material and portions of the dielectric to expose a remaining portion of the conductive material and a remaining portion of the dielectric. The remaining portion of the conductive material forms a second electrode of the capacitor. The remaining portion of the dielectric forms an insulator of the capacitor.

公开(公告)号：US20170117281A1

公开(公告)日：2017-04-27

申请号：US15399057

申请日：2017-01-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kevin K. Chan ,  Sivananda K. Kanakasabapathy ,  Babar A. Khan ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Theodorus E. Standaert ,  Xinhui Wang

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/06 ,  H01L29/51 ,  H01L21/84 ,  H01L29/04 ,  G06F17/50 ,  H01L27/12

CPC classification number: H01L27/10832 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/0733 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/10879 ,  H01L27/1203 ,  H01L27/1211 ,  H01L28/40 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/66181 ,  H01L29/945

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

公开(公告)号：US20170062410A1

公开(公告)日：2017-03-02

申请号：US14841530

申请日：2015-08-31

Applicant: Semiconductor Components Industries, LLC

Inventor： Gary H. LOECHELT

IPC: H01L27/06 ,  H01L29/866 ,  H01L21/306 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L49/02 ,  H01L29/872

CPC classification number: H01L27/0629 ,  H01L27/0727 ,  H01L27/0733 ,  H01L28/60 ,  H01L29/407 ,  H01L29/7393 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/866 ,  H01L29/872 ,  H03K17/08142

Abstract: A circuit can include a transistor, a capacitive element, and a rectifying element. The rectifying element and the capacitive element can be serially connected and coupled to the current-carrying terminals of the transistor. An electronic device may include part of the circuit. The electronic device can include a diode that includes a horizontally-oriented semiconductor member and a vertically-oriented semiconductor member having different conductivity types. The ends of the horizontally-oriented semiconductor and vertically-oriented semiconductor members physically contact each other. A process of forming an electronic device can include forming a semiconductor layer and forming a second semiconductor member. In a finished device, a diode includes a junction between dopants of first and second conductivity types within the semiconductor layer, within the semiconductor member, or at an interface between the semiconductor layer and the semiconductor member.

Abstract translation: 电路可以包括晶体管，电容元件和整流元件。 整流元件和电容元件可以串联连接并耦合到晶体管的载流端子。 电子设备可以包括电路的一部分。 电子器件可以包括二极管，其包括水平取向的半导体部件和具有不同导电类型的垂直取向的半导体部件。 水平取向的半导体和垂直取向的半导体部件的端部彼此物理接触。 形成电子器件的工艺可以包括形成半导体层并形成第二半导体部件。 在成品器件中，二极管包括在半导体层内，半导体元件内或半导体层与半导体元件之间的界面处的第一和第二导电类型的掺杂剂之间的结。

公开(公告)号：US20170025418A1

公开(公告)日：2017-01-26

申请号：US15285520

申请日：2016-10-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kevin K. Chan ,  Sivananda K. Kanakasabapathy ,  Babar A. Khan ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Theodorus E. Standaert ,  Xinhui Wang

IPC: H01L27/108

CPC classification number: H01L27/10832 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/0733 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/10879 ,  H01L27/1203 ,  H01L27/1211 ,  H01L28/40 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/66181 ,  H01L29/945

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract translation: 公开了一种集成的FinFET和深沟槽电容器结构及其制造方法。 该方法包括在绝缘体上硅（SOI）衬底上形成至少一个深沟槽电容器。 该方法还包括从SOI衬底同时从至少一个深沟槽电容器的材料和SOI散热片形成多晶硅鳍片。 该方法还包括在多晶硅鳍片上形成绝缘体层。 该方法还包括在多晶硅鳍片上的SOI散热片和绝缘体层上形成栅极结构。