公开(公告)号：US20230093450A1

公开(公告)日：2023-03-23

申请号：US18072457

申请日：2022-11-30

申请人： Applied Materials, Inc.

发明人： Tzu-shun YANG ,  Rui CHENG ,  Karthik JANAKIRAMAN ,  Zubin HUANG ,  Diwakar KEDLAYA ,  Meenakshi GUPTA ,  Srinivas GUGGILLA ,  Yung-chen LIN ,  Hidetaka OSHIO ,  Chao LI ,  Gene LEE

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3213

摘要： The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.

公开(公告)号：US20190115365A1

公开(公告)日：2019-04-18

申请号：US16151467

申请日：2018-10-04

申请人： Applied Materials, Inc.

发明人： Xinhai HAN ,  Deenesh PADHI ,  Er-Xuan PING ,  Srinivas GUGGILLA

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L21/02

摘要： Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

公开(公告)号：US20240090213A1

公开(公告)日：2024-03-14

申请号：US18238954

申请日：2023-08-28

申请人： Applied Materials, Inc.

发明人： Jialiang WANG ,  Soonil LEE ,  Eswaranand VENKATASUBRAMANIAN ,  Chang Seok KANG ,  Sanjay G. KAMATH ,  Abhijit B. MALLICK ,  Srinivas GUGGILLA ,  Amy CHILD ,  Sung-Kwan KANG ,  Balasubramanian PRANATHARTHIHARAN

IPC分类号： H10B41/35 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/67 ,  H10B43/10

CPC分类号： H10B41/35 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/67063 ,  H10B43/10 ,  H10B80/00

摘要： A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process and an etch process, wherein the first HAR structure has a critical dimension (CD) of between 150 nm and 250 nm, and the second HAR structure has a CD of between 250 nm and 400 nm.

公开(公告)号：US20200335338A1

公开(公告)日：2020-10-22

申请号：US16821759

申请日：2020-03-17

申请人： Applied Materials, Inc.

发明人： Tzu-Shun YANG ,  Rui CHENG ,  Karthik JANAKIRAMAN ,  Zubin HUANG ,  Diwakar KADLAYA ,  Meenakshi GUPTA ,  Srinivas GUGGILLA ,  Yung-chen LIN ,  Hidetaka OSHIO ,  Chao LI ,  Gene LEE

IPC分类号： H01L21/033

摘要： The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.

公开(公告)号：US20200321210A1

公开(公告)日：2020-10-08

申请号：US16797111

申请日：2020-02-21

申请人： Applied Materials, Inc.

发明人： Meenakshi GUPTA ,  Rui CHENG ,  Srinivas GUGGILLA ,  Karthik JANAKIRAMAN ,  Diwakar N. KEDLAYA ,  Zubin HUANG

IPC分类号： H01L21/027 ,  H01L21/32 ,  H01L21/02

摘要： Embodiments for processing a substrate are provided and include a method of trimming photoresist to provide photoresist profiles with smooth sidewall surfaces and to tune critical dimensions (CD) for the patterned features and/or a subsequently deposited dielectric layer. The method can include depositing a sacrificial structure layer on the substrate, depositing a photoresist on the sacrificial structure layer, and patterning the photoresist to produce a crude photoresist profile on the sacrificial structure layer. The method also includes trimming the photoresist with a plasma to produce a refined photoresist profile covering a first portion of the sacrificial structure layer while a second portion of the sacrificial structure layer is exposed, etching the second portion of the sacrificial structure layer to form patterned features disposed on the substrate, and depositing a dielectric layer on the patterned features.

公开(公告)号：US20200013597A1

公开(公告)日：2020-01-09

申请号：US16573265

申请日：2019-09-17

申请人： APPLIED MATERIALS, INC.

发明人： Anantha K. SUBRAMANI ,  Hanbing WU ,  Wei W. WANG ,  Ashish GOEL ,  Srinivas GUGGILLA ,  Lavinia NISTOR

IPC分类号： H01J37/34 ,  C23C14/34

摘要： Embodiments of a method and apparatus for co-sputtering multiple target materials are provided herein. In some embodiments, a process chamber including a substrate support to support a substrate; a plurality of cathodes coupled to a carrier and having a corresponding plurality of targets to be sputtered onto the substrate; and a process shield coupled to the carrier and extending between adjacent pairs of the plurality of targets.

公开(公告)号：US20200295041A1

公开(公告)日：2020-09-17

申请号：US16887433

申请日：2020-05-29

申请人： Applied Materials, Inc.

发明人： Xinhai HAN ,  Deenesh PADHI ,  Er-Xuan PING ,  Srinivas GUGGILLA

IPC分类号： H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/1157

摘要： Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

公开(公告)号：US20170098575A1

公开(公告)日：2017-04-06

申请号：US15285011

申请日：2016-10-04

申请人： APPLIED MATERIALS, INC.

发明人： Sree Rangasai V. KESAPRAGADA ,  Kevin MORAES ,  Srinivas GUGGILLA ,  He REN ,  Mehul NAIK ,  David THOMPSON ,  Weifeng YE ,  Yana CHENG ,  Yong CAO ,  Xianmin TANG ,  Paul F. MA ,  Deenesh PADHI

IPC分类号： H01L21/768 ,  H01L21/02

CPC分类号： H01L21/76832 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834

摘要： In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：US20160372319A1

公开(公告)日：2016-12-22

申请号：US14744688

申请日：2015-06-19

申请人： APPLIED MATERIALS, INC.

发明人： Weimin ZENG ,  Thanh X. NGUYEN ,  Yana CHENG ,  Yong CAO ,  Daniel Lee DIEHL ,  Srinivas GUGGILLA ,  Rongjun WANG ,  Xianmin TANG

IPC分类号： H01L21/02

CPC分类号： H01L21/0234 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02266

摘要： In some embodiments a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) depositing a dielectric layer to a first thickness atop a first surface of the substrate via a physical vapor deposition process; (b) providing a first plasma forming gas to a processing region of the physical vapor deposition process chamber, wherein the first plasma forming gas comprises hydrogen but not carbon; (c) providing a first amount of bias power to a substrate support to form a first plasma from the first plasma forming gas within the processing region of the physical vapor deposition process chamber; (d) exposing the dielectric layer to the first plasma; and (e) repeating (a)-(d) to deposit the dielectric film to a final thickness.

摘要翻译： 在一些实施例中，处理设置在物理气相沉积处理室中的衬底支架顶上的衬底的方法包括：（a）通过物理气相沉积工艺在介质的第一表面顶部沉积介电层至第一厚度; （b）向所述物理气相沉积处理室的处理区域提供第一等离子体形成气体，其中所述第一等离子体形成气体包括氢而不是碳; （c）向所述衬底支撑件提供第一量的偏置功率以从所述物理气相沉积处理室的处理区域内的所述第一等离子体形成气体形成第一等离子体; （d）将介电层暴露于第一等离子体; 和（e）重复（a） - （d）将电介质膜沉积到最终厚度。

公开(公告)号：US20200335339A1

公开(公告)日：2020-10-22

申请号：US16867095

申请日：2020-05-05

申请人： Applied Materials, Inc.

发明人： Tzu-shun YANG ,  Rui CHENG ,  Karthik JANAKIRAMAN ,  Zubin HUANG ,  Diwakar KEDLAYA ,  Meenakshi GUPTA ,  Srinivas GUGGILLA ,  Yung-chen LIN ,  Hidetaka OSHIO ,  Chao LI ,  Gene LEE

IPC分类号： H01L21/033

摘要： The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.