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公开(公告)号:US20240395561A1
公开(公告)日:2024-11-28
申请号:US18637181
申请日:2024-04-16
Applicant: Applied Materials, Inc.
IPC: H01L21/311 , H01J37/32
Abstract: A method for patterning a boron-containing hard mask includes patterning an oxide hard mask formed on a boron-containing hard mask, and patterning the boron-containing hard mask using the patterned oxide hard mask, wherein the oxide hard mask comprises silicon oxide (SiO2), the boron-containing hard mask is doped with one or more metal elements, and the patterning of the boron-containing hard mask comprises etching the boron-containing hard mask through openings of the patterned oxide hard mask using an etching gas mixture comprising chlorine (Cl2), hydrogen bromide (HBr), and oxygen (O2).
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公开(公告)号:US20240162057A1
公开(公告)日:2024-05-16
申请号:US18379048
申请日:2023-10-11
Applicant: Applied Materials, Inc.
CPC classification number: H01L21/67069 , H01L21/02126 , H01L21/0234
Abstract: A method for spacer patterning includes performing a deposition process, the deposition process comprising conformally depositing an over layer over a spacer layer as deposited on top surfaces of a patterned mandrel layer and on sidewalls of the patterned mandrel layer, and performing an etch process using a fluorine containing etching gas. The etch process includes a post-deposition breakthrough process, removing portions of the over layer on the top surfaces of the patterned mandrel layer, and a main-etch process, removing shoulder portions of the over layer and shoulder portions of the spacer layer.
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公开(公告)号:US20230093450A1
公开(公告)日:2023-03-23
申请号:US18072457
申请日:2022-11-30
Applicant: Applied Materials, Inc.
Inventor: Tzu-shun YANG , Rui CHENG , Karthik JANAKIRAMAN , Zubin HUANG , Diwakar KEDLAYA , Meenakshi GUPTA , Srinivas GUGGILLA , Yung-chen LIN , Hidetaka OSHIO , Chao LI , Gene LEE
IPC: H01L21/033 , H01L21/311 , H01L21/3213
Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.
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公开(公告)号:US20200335338A1
公开(公告)日:2020-10-22
申请号:US16821759
申请日:2020-03-17
Applicant: Applied Materials, Inc.
Inventor: Tzu-Shun YANG , Rui CHENG , Karthik JANAKIRAMAN , Zubin HUANG , Diwakar KADLAYA , Meenakshi GUPTA , Srinivas GUGGILLA , Yung-chen LIN , Hidetaka OSHIO , Chao LI , Gene LEE
IPC: H01L21/033
Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.
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公开(公告)号:US20240282631A1
公开(公告)日:2024-08-22
申请号:US18419526
申请日:2024-01-22
Applicant: Applied Materials, Inc.
Inventor: Xi CEN , Kai WU , Yao XU , Yang LI , Meng ZHU , Insu HA , Jianqiu GUO , Chao LI , Rongjun WANG , Xianmin TANG
IPC: H01L21/768 , H01L21/02 , H01L21/285
CPC classification number: H01L21/76879 , H01L21/02068 , H01L21/28568 , H01L21/76843
Abstract: A method of filling a via having a necking point includes performing a pre-clean process to remove residues from an exposed surface of a metal layer at a bottom of a via and recover inner surfaces of the via, wherein the via is formed within a dielectric layer and has a necking point protruding within the via, performing a selective deposition process to partially fill the via with metal fill material from the exposed surface of the metal layer below the necking point, performing a liner deposition process to form a liner layer on exposed inner surfaces of the via, and performing a metal fill process to fill the via with the metal fill material.
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公开(公告)号:US20220359201A1
公开(公告)日:2022-11-10
申请号:US17712955
申请日:2022-04-04
Applicant: Applied Materials, Inc.
IPC: H01L21/033 , H01L21/311
Abstract: A method for forming a metal containing feature includes performing a deposition process, the deposition process comprising conformally depositing an over layer on top surfaces of a patterned mandrel layer and over a spacer layer on sidewalls of the patterned mandrel layer, and performing an etch process, the etch process comprising removing the over layer from the top surfaces of the patterned mandrel layer and shoulder portions of the spacer layer, and removing the shoulder portions of the spacer layer, using a fluorine containing etching gas.
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公开(公告)号:US20200335339A1
公开(公告)日:2020-10-22
申请号:US16867095
申请日:2020-05-05
Applicant: Applied Materials, Inc.
Inventor: Tzu-shun YANG , Rui CHENG , Karthik JANAKIRAMAN , Zubin HUANG , Diwakar KEDLAYA , Meenakshi GUPTA , Srinivas GUGGILLA , Yung-chen LIN , Hidetaka OSHIO , Chao LI , Gene LEE
IPC: H01L21/033
Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.
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