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    MULTI-LAYER STACKS FOR 3D NAND EXTENDABILITY
    5.
    发明申请
    MULTI-LAYER STACKS FOR 3D NAND EXTENDABILITY 审中-公开

    公开(公告)号：US20200295041A1

    公开(公告)日：2020-09-17

    申请号：US16887433

    申请日：2020-05-29

    申请人： Applied Materials, Inc.

    发明人： Xinhai HAN ,  Deenesh PADHI ,  Er-Xuan PING ,  Srinivas GUGGILLA

    IPC分类号： H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/1157

    摘要： Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

    PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION OF FILMS FOR IMPROVED VERTICAL ETCH PERFORMANCE IN 3D NAND MEMORY DEVICES
    8.
    发明申请
    PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION OF FILMS FOR IMPROVED VERTICAL ETCH PERFORMANCE IN 3D NAND MEMORY DEVICES 审中-公开
    等离子体增强化学气相沉积在3D NAND存储器件中改善垂直蚀刻性能的膜

    公开(公告)号：US20160293609A1

    公开(公告)日：2016-10-06

    申请号：US15063569

    申请日：2016-03-08

    申请人： Applied Materials, Inc.

    发明人： Praket P. JHA ,  Allen KO ,  Xinhai HAN ,  Thomas Jongwan KWON ,  Bok Hoen KIM ,  Byung Ho KIL ,  Ryeun KIM ,  Sang Hyuk KIM

    IPC分类号： H01L27/115 ,  H01L21/311 ,  C23C16/455 ,  C23C16/40 ,  C23C16/34 ,  H01L29/423 ,  H01L21/02

    CPC分类号： C23C16/345 ,  C23C16/401 ,  C23C16/45523 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/31116 ,  H01L27/11556 ,  H01L27/11582

    摘要： Implementations of the present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, 3D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.

    摘要翻译： 本公开的实施方式一般涉及包含高纵横比特征定义的薄膜及其形成方法。 随着栅极高度的增加，3D NAND栅极堆叠受到更高的纵横比蚀刻。 由于蚀刻技术的当前局限性，垂直蚀刻轮廓通常随着进入栅极堆叠的深度而增加。 本发明人设计了一种独特的沉积方案，其通过新颖的等离子体增强化学气相沉积（PECVD）膜沉积方法来补偿深沟槽中的蚀刻性能降低。 本发明人已经发现，通过分级沉积膜（例如，氮化硅）的各种性质（例如，折射率，膜的应力，膜中的掺杂剂浓度），可以通过补偿变化来实现更均匀的蚀刻轮廓 干和湿蚀刻速率。