公开(公告)号：US20190027403A1

公开(公告)日：2019-01-24

申请号：US16140342

申请日：2018-09-24

Applicant: APPLIED MATERIALS, INC.

Inventor： Sree Rangasai V. KESAPRAGADA ,  Kevin MORAES ,  Srinivas GUGGILLA ,  He REN ,  Mehul NAIK ,  David THOMPSON ,  Weifeng YE ,  Yana CHENG ,  Yong CAO ,  Xianmin TANG ,  Paul F. MA ,  Deenesh PADHI

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76832 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：US20210233802A1

公开(公告)日：2021-07-29

申请号：US17227354

申请日：2021-04-11

Applicant: APPLIED MATERIALS, INC.

Inventor： Felix DENG ,  Yueh Sheng OW ,  Tuck Foong KOH ,  Nuno Yen-Chu CHEN ,  Yuichi WADA ,  Sree Rangasai V. KESAPRAGADA ,  Clinton GOH

IPC: H01L21/762 ,  H01L21/67

Abstract: Methods and apparatus for cleaving a substrate in a semiconductor chamber. The semiconductor chamber pressure is adjusted to a process pressure, a substrate is then heated to a nucleation temperature of ions implanted in the substrate, the temperature of the substrate is then adjusted below the nucleation temperature of the ions, and the temperature is maintained until cleaving of the substrate occurs. Microwaves may be used to provide heating of the substrate for the processes. A cleaving sensor may be used for detection of successful cleaving by detecting pressure changes, acoustic emissions, changes within the substrate, and/or residual gases given off by the implanted ions when the cleaving occurs.

公开(公告)号：US20210217656A1

公开(公告)日：2021-07-15

申请号：US17217179

申请日：2021-03-30

Applicant: APPLIED MATERIALS, INC.

Inventor： Felix DENG ,  Yueh Sheng OW ,  Tuck Foong KOH ,  Nuno Yen-Chu CHEN ,  Yuichi WADA ,  Sree Rangasai V. KESAPRAGADA ,  Clinton GOH

IPC: H01L21/762 ,  H01L21/67

Abstract: Methods and apparatus for cleaving a substrate in a semiconductor chamber. The semiconductor chamber pressure is adjusted to a process pressure, a substrate is then heated to a nucleation temperature of ions implanted in the substrate, the temperature of the substrate is then adjusted below the nucleation temperature of the ions, and the temperature is maintained until cleaving of the substrate occurs. Microwaves may be used to provide heating of the substrate for the processes. A cleaving sensor may be used for detection of successful cleaving by detecting pressure changes, acoustic emissions, changes within the substrate, and/or residual gases given off by the implanted ions when the cleaving occurs.

公开(公告)号：US20170098575A1

公开(公告)日：2017-04-06

申请号：US15285011

申请日：2016-10-04

Applicant: APPLIED MATERIALS, INC.

Inventor： Sree Rangasai V. KESAPRAGADA ,  Kevin MORAES ,  Srinivas GUGGILLA ,  He REN ,  Mehul NAIK ,  David THOMPSON ,  Weifeng YE ,  Yana CHENG ,  Yong CAO ,  Xianmin TANG ,  Paul F. MA ,  Deenesh PADHI

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76832 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：US20150255329A1

公开(公告)日：2015-09-10

申请号：US14201728

申请日：2014-03-07

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Mehul B. NAIK ,  Yong CAO ,  Sree Rangasai V. KESAPRAGADA ,  Mei-Yee SHEK ,  Yana CHENG

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76841 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/321 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849

Abstract: Methods for forming a passivation protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming passivation protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal capping layer on a metal line bounded by a dielectric bulk insulating layer in an interconnection structure formed on a substrate in a processing chamber incorporated in a multi-chamber processing system, in-situ forming a barrier layer on the substrate in the processing chamber; wherein the barrier layer is a metal dielectric layer, and forming a dielectric capping layer on the barrier layer in the multi-chamber processing system.

Abstract translation: 提供了在形成在互连结构中的绝缘材料中的金属线层上形成钝化保护结构的方法。 在一个实施例中，用于在半导体器件的互连结构中的金属线上形成钝化保护的方法包括在处理中形成在基板上的互连结构中的介电体绝缘层界定的金属线上选择性地形成金属覆盖层 结合在多腔室处理系统中，在处理室中的基底上原位形成阻挡层; 其中所述阻挡层是金属介电层，并且在所述多室处理系统中的阻挡层上形成电介质覆盖层。