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    METHOD TO REDUCE TRAP-INDUCED CAPACITANCE IN INTERCONNECT DIELECTRIC BARRIER STACK
    2.
    发明申请
    METHOD TO REDUCE TRAP-INDUCED CAPACITANCE IN INTERCONNECT DIELECTRIC BARRIER STACK 审中-公开
    减少互连电介质堆叠中的陷波电容的方法

    公开(公告)号：US20170005041A1

    公开(公告)日：2017-01-05

    申请号：US15186436

    申请日：2016-06-18

    Applicant: Applied Materials, Inc.

    Inventor： He REN ,  Mehul B. NAIK ,  Yong CAO ,  Yana CHENG ,  Weifeng YE

    IPC: H01L23/532 ,  H01L21/02 ,  H01L23/528 ,  H01L21/768

    CPC classification number: H01L21/02167 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/76826 ,  H01L21/76832

    Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.

    Abstract translation: 本公开提供了形成在衬底上的互连和用于在衬底上形成互连的方法。 在一个实施例中，用于在衬底上形成互连的方法包括在衬底上沉积阻挡层，在阻挡层上沉积过渡层，以及在过渡层上沉积蚀刻停止层，其中过渡层共享共同 元件，并且其中所述过渡层与所述蚀刻停止层共享公共元件。

    METHODS FOR DEPOSITING DIELECTRIC FILMS VIA PHYSICAL VAPOR DEPOSITION PROCESSES
    4.
    发明申请
    METHODS FOR DEPOSITING DIELECTRIC FILMS VIA PHYSICAL VAPOR DEPOSITION PROCESSES 有权
    通过物理蒸发沉积工艺沉积介电膜的方法

    公开(公告)号：US20160372319A1

    公开(公告)日：2016-12-22

    申请号：US14744688

    申请日：2015-06-19

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Weimin ZENG ,  Thanh X. NGUYEN ,  Yana CHENG ,  Yong CAO ,  Daniel Lee DIEHL ,  Srinivas GUGGILLA ,  Rongjun WANG ,  Xianmin TANG

    IPC: H01L21/02

    CPC classification number: H01L21/0234 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02266

    Abstract: In some embodiments a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) depositing a dielectric layer to a first thickness atop a first surface of the substrate via a physical vapor deposition process; (b) providing a first plasma forming gas to a processing region of the physical vapor deposition process chamber, wherein the first plasma forming gas comprises hydrogen but not carbon; (c) providing a first amount of bias power to a substrate support to form a first plasma from the first plasma forming gas within the processing region of the physical vapor deposition process chamber; (d) exposing the dielectric layer to the first plasma; and (e) repeating (a)-(d) to deposit the dielectric film to a final thickness.

    Abstract translation: 在一些实施例中，处理设置在物理气相沉积处理室中的衬底支架顶上的衬底的方法包括：（a）通过物理气相沉积工艺在介质的第一表面顶部沉积介电层至第一厚度; （b）向所述物理气相沉积处理室的处理区域提供第一等离子体形成气体，其中所述第一等离子体形成气体包括氢而不是碳; （c）向所述衬底支撑件提供第一量的偏置功率以从所述物理气相沉积处理室的处理区域内的所述第一等离子体形成气体形成第一等离子体; （d）将介电层暴露于第一等离子体; 和（e）重复（a） - （d）将电介质膜沉积到最终厚度。

    METHODS FOR FORMING PASSIVATION PROTECTION FOR AN INTERCONNECTION STRUCTURE
    5.
    发明申请
    METHODS FOR FORMING PASSIVATION PROTECTION FOR AN INTERCONNECTION STRUCTURE 有权
    用于形成互连结构的钝化保护的方法

    公开(公告)号：US20150255329A1

    公开(公告)日：2015-09-10

    申请号：US14201728

    申请日：2014-03-07

    Applicant: Applied Materials, Inc.

    Inventor： He Ren ,  Mehul B. NAIK ,  Yong CAO ,  Sree Rangasai V. KESAPRAGADA ,  Mei-Yee SHEK ,  Yana CHENG

    IPC: H01L21/768 ,  H01L21/02

    CPC classification number: H01L21/76841 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/321 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849

    Abstract: Methods for forming a passivation protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming passivation protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal capping layer on a metal line bounded by a dielectric bulk insulating layer in an interconnection structure formed on a substrate in a processing chamber incorporated in a multi-chamber processing system, in-situ forming a barrier layer on the substrate in the processing chamber; wherein the barrier layer is a metal dielectric layer, and forming a dielectric capping layer on the barrier layer in the multi-chamber processing system.

    Abstract translation: 提供了在形成在互连结构中的绝缘材料中的金属线层上形成钝化保护结构的方法。 在一个实施例中，用于在半导体器件的互连结构中的金属线上形成钝化保护的方法包括在处理中形成在基板上的互连结构中的介电体绝缘层界定的金属线上选择性地形成金属覆盖层 结合在多腔室处理系统中，在处理室中的基底上原位形成阻挡层; 其中所述阻挡层是金属介电层，并且在所述多室处理系统中的阻挡层上形成电介质覆盖层。

    METHODS FOR THIN FILM MATERIAL DEPOSITION USING REACTIVE PLASMA-FREE PHYSICAL VAPOR DEPOSITION
    7.
    发明申请
    METHODS FOR THIN FILM MATERIAL DEPOSITION USING REACTIVE PLASMA-FREE PHYSICAL VAPOR DEPOSITION 审中-公开

    公开(公告)号：US20170125215A1

    公开(公告)日：2017-05-04

    申请号：US14986168

    申请日：2015-12-31

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Yana CHENG ,  Zhefeng LI ,  Chi Hong CHING ,  Yong CAO ,  Rongjun WANG

    IPC: H01J37/32 ,  C23C14/34

    Abstract: Methods are disclosed for depositing a thin film of compound material on a substrate. In some embodiments, a method of depositing a layer of compound material on a substrate include: flowing a reactive gas into a plasma processing chamber having a substrate to be sputter deposited disposed therein in opposition to a sputter target comprising a metal; exciting the reactive gas into a reactive gas plasma to react with the sputter target and to form a first layer of compound material thereon; flowing an inert gas into the plasma processing chamber; and exciting the inert gas into a plasma to sputter a second layer of the compound material onto the substrate directly from the first layer of compound material. The cycles of target poisoning and sputtering may be repeated until a compound material layer of appropriate thickness has been formed on the substrate.

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