公开(公告)号：US20240379420A1

公开(公告)日：2024-11-14

申请号：US18781633

申请日：2024-07-23

Applicant: APPLIED MATERIALS, INC.

Inventor： Shi YOU ,  He REN ,  Naomi YOSHIDA ,  Nikolaos BEKIARIS ,  Mehul NAIK ,  Martin Jay SEAMONS ,  Jingmei LIANG ,  Mei-Yee SHEK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/67

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material

公开(公告)号：US20190157145A1

公开(公告)日：2019-05-23

申请号：US16252100

申请日：2019-01-18

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Feiyue MA ,  Yu LEI ,  Kai WU ,  Mehul B. NAIK ,  Zhiyuan WU ,  Vikash BANTHIA ,  Hua AI

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/522

Abstract: Interconnects and methods for forming interconnects are described and disclosed herein. The interconnect contains a stack formed on a substrate having a via and a trench formed therein, a first metal formed from a first material of a first type deposited in the via, and a second metal formed from a second material of a second type deposited in the trench.

公开(公告)号：US20190051557A1

公开(公告)日：2019-02-14

申请号：US16102543

申请日：2018-08-13

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Sean S. KANG ,  Keith Tatseun WONG ,  He REN ,  Mehul B. NAIK ,  Ellie Y. YIEH ,  Srinivas D. NEMANI

IPC: H01L21/768 ,  H01L23/532

Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.

公开(公告)号：US20170005041A1

公开(公告)日：2017-01-05

申请号：US15186436

申请日：2016-06-18

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Mehul B. NAIK ,  Yong CAO ,  Yana CHENG ,  Weifeng YE

IPC: H01L23/532 ,  H01L21/02 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L21/02167 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/76826 ,  H01L21/76832

Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.

Abstract translation: 本公开提供了形成在衬底上的互连和用于在衬底上形成互连的方法。 在一个实施例中，用于在衬底上形成互连的方法包括在衬底上沉积阻挡层，在阻挡层上沉积过渡层，以及在过渡层上沉积蚀刻停止层，其中过渡层共享共同 元件，并且其中所述过渡层与所述蚀刻停止层共享公共元件。

公开(公告)号：US20160211172A1

公开(公告)日：2016-07-21

申请号：US15084104

申请日：2016-03-29

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Mehul B. NAIK

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/764 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32136 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76889

Abstract: Embodiments described herein relate to methods for forming an air gap interconnect. A metal spacer layer is conformally deposited on a substrate having mandrel structures formed thereon. The metal spacer layer is etched to form spacer features and the mandrel structures are removed from the substrate. Various other dielectric deposition, patterning and etching steps may be performed to desirably pattern materials present on the substrate. Ultimately, a trench is formed between adjacent spacer features and a capping layer is deposited over the trench to form an air gap between the adjacent spacer features. For packaging purposes, an interconnect via may be configured to contact at least one of the spacer features adjacent the air gap.

公开(公告)号：US20240213088A1

公开(公告)日：2024-06-27

申请号：US18595951

申请日：2024-03-05

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Hao JIANG ,  Shi YOU ,  Mehul B. NAIK

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76879

Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 μΩ·cm or less.

公开(公告)号：US20220359224A1

公开(公告)日：2022-11-10

申请号：US17307383

申请日：2021-05-04

Applicant: Applied Materials, Inc.

Inventor： Hao JIANG ,  Chi LU ,  He REN ,  Mehul NAIK

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/67 ,  H01J37/32

Abstract: Methods and apparatus for processing a substrate are provided. For example, a method of processing a substrate comprises supplying oxygen (O2) into a processing volume of an etch chamber to react with a silicon-based hardmask layer atop a base layer of ruthenium to form a covering of an SiO-like material over the silicon-based hardmask layer and etching the base layer of ruthenium using at least one of O2 or chloride (Cl2) while supplying nitrogen (N2) to sputter some of the SiO-like material onto an exposed ruthenium sidewall created during etching.

公开(公告)号：US20220285212A1

公开(公告)日：2022-09-08

申请号：US17193994

申请日：2021-03-05

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Hao JIANG ,  Shi YOU ,  Mehul B. NAIK

IPC: H01L21/768

Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 μΩ·cm or less.

公开(公告)号：US20200027782A1

公开(公告)日：2020-01-23

申请号：US16037985

申请日：2018-07-17

Applicant: Applied Materials, Inc.

Inventor： Hao JIANG ,  He REN ,  Hao CHEN ,  Mehul B. NAIK

IPC: H01L21/768 ,  H01L21/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

Abstract: Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.

公开(公告)号：US20180315650A1

公开(公告)日：2018-11-01

申请号：US15498024

申请日：2017-04-26

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Feiyue MA ,  Yu LEI ,  Kai WU ,  Mehul B. NAIK ,  Zhiyuan WU ,  Vikash BANTHIA ,  Hua AI

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76879 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257

Abstract: Embodiments of the present disclosure generally relate an interconnect formed on a substrate and a method of forming the interconnect thereon. In an embodiment, a via and trench in a stack formed on the substrate. A bottom of the via is pre-treated using a first pre-treatment procedure. A sidewall of the via is pre-treated using a second pre-treatment procedure. A first metal fill material of a first type is deposited on the stack, in the via. A second metal fill material of a second type is deposited on the stack, in the trench.