公开(公告)号：US20180315650A1

公开(公告)日：2018-11-01

申请号：US15498024

申请日：2017-04-26

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Feiyue MA ,  Yu LEI ,  Kai WU ,  Mehul B. NAIK ,  Zhiyuan WU ,  Vikash BANTHIA ,  Hua AI

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76879 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257

Abstract: Embodiments of the present disclosure generally relate an interconnect formed on a substrate and a method of forming the interconnect thereon. In an embodiment, a via and trench in a stack formed on the substrate. A bottom of the via is pre-treated using a first pre-treatment procedure. A sidewall of the via is pre-treated using a second pre-treatment procedure. A first metal fill material of a first type is deposited on the stack, in the via. A second metal fill material of a second type is deposited on the stack, in the trench.

公开(公告)号：US20190157145A1

公开(公告)日：2019-05-23

申请号：US16252100

申请日：2019-01-18

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Feiyue MA ,  Yu LEI ,  Kai WU ,  Mehul B. NAIK ,  Zhiyuan WU ,  Vikash BANTHIA ,  Hua AI

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/522

Abstract: Interconnects and methods for forming interconnects are described and disclosed herein. The interconnect contains a stack formed on a substrate having a via and a trench formed therein, a first metal formed from a first material of a first type deposited in the via, and a second metal formed from a second material of a second type deposited in the trench.