公开(公告)号：US20210317580A1

公开(公告)日：2021-10-14

申请号：US16848784

申请日：2020-04-14

Applicant: APPLIED MATERIALS, INC.

Inventor： Shi YOU ,  He REN ,  Naomi YOSHIDA ,  Nikolaos BEKIARIS ,  Mehul NAIK ,  Martin Jay SEAMONS ,  Jingmei LIANG ,  Mei-Yee SHEK

IPC: C23C16/56 ,  H01L21/768

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material

公开(公告)号：US20230187276A1

公开(公告)日：2023-06-15

申请号：US18108338

申请日：2023-02-10

Applicant: APPLIED MATERIALS, INC.

Inventor： Shi YOU ,  He REN ,  Naomi YOSHIDA ,  Nikolaos BEKIARIS ,  Mehul NAIK ,  Jay Martin SEAMONS ,  Jingmei LIANG ,  Mei-Yee SHEK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L21/76837 ,  H01L21/76828 ,  H01L21/76826 ,  H01L21/02337 ,  H01L21/76825 ,  H01L21/02323 ,  H01L21/76834 ,  H01L21/67103 ,  H01L21/02326

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material

公开(公告)号：US20210233765A1

公开(公告)日：2021-07-29

申请号：US17153450

申请日：2021-01-20

Applicant: Applied Materials, Inc.

Inventor： Naomi YOSHIDA ,  He REN ,  Hao JIANG ,  Chenfei SHEN ,  Chi-Chou LIN ,  Hao CHEN ,  Xuesong LU ,  Mehul B. NAIK

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L29/66 ,  B08B5/02

Abstract: Embodiments of the present disclosure generally relate to methods of cleaning a structure and methods of depositing a capping layer in a structure. The method of cleaning a structure includes suppling a cleaning gas, including a first gas including nitrogen (N) and a second gas including fluorine (F), to a bottom surface of a structure. The cleaning gas removes unwanted metal oxide and etch residue from the bottom surface of the structure. The method of depositing a capping layer includes depositing the capping layer over the bottom surface of the structure. The methods described herein reduce the amount of unwanted metal oxides and residue, which improves adhesion of deposited capping layers.

公开(公告)号：US20180061978A1

公开(公告)日：2018-03-01

申请号：US15804691

申请日：2017-11-06

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Naomi YOSHIDA ,  Theresa Kramer GUARINI ,  Sung Won JUN ,  Vanessa PENA ,  Errol Antonio C. SANCHEZ ,  Benjamin COLOMBEAU ,  Michael CHUDZIK ,  Bingxi Sun WOOD ,  Nam Sung KIM

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78642

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US20220173220A1

公开(公告)日：2022-06-02

申请号：US17672788

申请日：2022-02-16

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Nam Sung KIM ,  Bingxi Sun WOOD ,  Naomi YOSHIDA ,  Sheng-Chin KUNG ,  Miao JIN

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L29/775 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: Embodiments provide methods for forming nanowire structures, such as, for example, horizontal gate-all-around (hGAA) structures. In one embodiment, a method includes selectively etching material from a stack disposed on a material layer located on a substrate with a plasma to create recesses on each of first and second sides of the stack and depositing a dielectric material on the first and second sides. The stack includes repeating pairs of first and second layers. The method also includes removing the dielectric material from the first and second sides, where the dielectric material remains in the recesses of the first and second sides, and selectively depositing a stressor layer on regions of the first and second sides which are unprotected by the dielectric material to form gaps between the stressor layer and the dielectric material remaining in the recesses of the first and second sides.

公开(公告)号：US20170040159A1

公开(公告)日：2017-02-09

申请号：US15230218

申请日：2016-08-05

Applicant: Applied Materials, Inc. ,  The Regents of the University of California

Inventor： Jessica S. KACHIAN ,  Naomi YOSHIDA ,  Mei CHANG ,  Mary EDMONDS ,  Andrew C. KUMMEL ,  Sang Wook PARK ,  Hyunwoong KIM

IPC: H01L21/02

CPC classification number: H01L21/0228 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02299 ,  H01L21/02301 ,  H01L21/02304

Abstract: Embodiments described herein provide a self-limiting and saturating Si—Ox bilayer process which does not require the use of a plasma or catalyst and that does not lead to undesirable substrate oxidation. Methods of the disclosure do not produce SiO2, but instead produce a saturated Si—Ox film with —OH termination to make substrate surfaces highly reactive towards metal ALD precursors to seed high nucleation and growth of gate oxide ALD materials.

Abstract translation: 本文描述的实施方案提供了自限制和饱和的Si-Ox双层方法，其不需要使用等离子体或催化剂，并且不会导致不希望的底物氧化。 本公开的方法不产生SiO 2，而是产生具有-OH终止的饱和Si-Ox膜，以使底物表面对金属ALD前体具有高度反应性，以使栅极氧化物ALD材料的高成核和生长。

公开(公告)号：US20160336405A1

公开(公告)日：2016-11-17

申请号：US15152273

申请日：2016-05-11

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Naomi YOSHIDA ,  Theresa Kramer GUARINI ,  Sung Won JUN ,  Vanessa PENA ,  Errol Antonio C. SANCHEZ ,  Benjamin COLOMBEAU ,  Michael CHUDZIK ,  Bingxi WOOD ,  Nam Sung KIM

IPC: H01L29/15 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/45 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78642

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Abstract translation: 本文描述的实施例通常涉及用于水平门全周（hGAA）隔离和鳍场效应晶体管（FinFET）隔离的方法和器件结构。 可以在衬底上形成包括布置在交替堆叠的层中的不同材料的超晶格结构。 在一个实施例中，超晶格结构的至少一个层可以被氧化以形成邻近衬底的掩埋氧化物层。

公开(公告)号：US20200035822A1

公开(公告)日：2020-01-30

申请号：US16592362

申请日：2019-10-03

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Naomi YOSHIDA ,  Theresa Kramer GUARINI ,  Sung Won JUN ,  Vanessa PENA ,  Errol Antonio C. SANCHEZ ,  Benjamin COLOMBEAU ,  Michael CHUDZIK ,  Bingxi WOOD ,  Nam Sung KIM

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US20180019116A1

公开(公告)日：2018-01-18

申请号：US15714162

申请日：2017-09-25

Applicant: Applied Materials, Inc. ,  The Regents of the University of California

Inventor： Jessica S. KACHIAN ,  Naomi YOSHIDA ,  Mei CHANG ,  Mary EDMONDS ,  Andrew C. KUMMEL ,  Sang Wook PARK ,  Hyunwoong KIM

IPC: H01L21/02

Abstract: Embodiments described herein provide a self-limiting and saturating Si—Ox bilayer process which does not require the use of a plasma or catalyst and that does not lead to undesirable substrate oxidation. Methods of the disclosure do not produce SiO2, but instead produce a saturated Si—Ox film with —OH termination to make substrate surfaces highly reactive towards metal ALD precursors to seed high nucleation and growth of gate oxide ALD materials.

公开(公告)号：US20170309719A1

公开(公告)日：2017-10-26

申请号：US15494981

申请日：2017-04-24

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Nam Sung KIM ,  Bingxi Sun WOOD ,  Naomi YOSHIDA ,  Sheng-Chin KUNG ,  Miao JIN

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.