公开(公告)号：US20100237494A1

公开(公告)日：2010-09-23

申请号：US12796011

申请日：2010-06-08

申请人： Young Do Kweon ,  Tongbi Jiang

发明人： Young Do Kweon ,  Tongbi Jiang

IPC分类号： H01L23/538

CPC分类号： H01L24/742 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/566 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/11 ,  H01L24/12 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54486 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/11013 ,  H01L2224/11015 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/7598 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/384 ,  H01L2924/00 ,  H01L2224/05599

摘要： Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

摘要翻译： 本文公开了在半导体工件上形成多个微电子器件的微电子器件和方法。 一种这样的方法包括将多个第一互连元件放置在半导体工件的一侧上，在工件侧面上形成层，通过加热第一互连元件来重塑第一互连元件，以及将多个第一互连元件的第一部分 单独的第二互连元件到相应的第一互连元件，其中所述单个第二互连元件的第二部分被暴露。

公开(公告)号：US20090095502A1

公开(公告)日：2009-04-16

申请号：US11870583

申请日：2007-10-11

申请人： VIRENDRA R. JADHAV ,  KRYSTYNA W. SEMKOW ,  KAMALESH K. SRIVASTAVA ,  BRIAN R. SUNDLOF

发明人： VIRENDRA R. JADHAV ,  KRYSTYNA W. SEMKOW ,  KAMALESH K. SRIVASTAVA ,  BRIAN R. SUNDLOF

IPC分类号： H01B5/02 ,  H01L21/60

CPC分类号： H01L24/13 ,  H01L23/562 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2224/16235 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/384 ,  Y10T156/10 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions

摘要翻译： 提供了一种多层柱及其制造方法。 多层柱用作芯片和基板之间的互连。 支柱具有至少一个低强度，高延展性变形区域，其被配置为吸收在芯片组装和热偏移期间施加的力

公开(公告)号：US06399182B1

公开(公告)日：2002-06-04

申请号：US09548093

申请日：2000-04-12

申请人： Erich K. Rubel ,  Jonathan H. Harris ,  Gabriel M. Carrasco

发明人： Erich K. Rubel ,  Jonathan H. Harris ,  Gabriel M. Carrasco

IPC分类号： H01L23495

CPC分类号： H01L24/83 ,  H01L23/13 ,  H01L24/32 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32057 ,  H01L2224/8314 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/384 ,  Y10T29/496 ,  Y10T29/49996 ,  Y10T428/12576 ,  Y10T428/12611 ,  Y10T428/12889 ,  Y10T428/12931 ,  Y10T428/24537 ,  Y10T428/2457 ,  Y10T428/24942 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2924/00

摘要： A substrate for a microelectronic package comprising a substrate that has grooves on a surface for bonding. A method for preparing a substrate for bonding comprising forming a grooved surface in the substrate for accepting a die for bonding, wherein the grooves are of sufficient size to provide a substantially uniform die bond, but no so large as to nullify the thermal path to the underlying substrate. A method for forming a bond between a substrate and a die comprising: providing a substrate and a die, wherein the substrate has grooves formed in a surface area for accepting the die for bonding and having a metallization thereon sufficient to form a eutectic bond with the die having a gold metallization thereon; and forming a eutectic bond between the substrate and the die comprising heating the substrate, contacting the metallized grooved surface of the substrate to the gold metallized surface of the die, scrubbing the die onto the substrate by moving the die back and forth while maintaining contact, and cooling the substrate and die. A microelectronic structure comprising a substrate and a die, wherein the substrate has grooves on a surface adapted for bonding with the die, and wherein a bond is formed between the substrate and the die.

摘要翻译： 一种用于微电子封装的衬底，包括在表面上具有用于接合的沟槽的衬底。 一种用于制备用于接合的基底的方法，包括在所述基底中形成用于接受用于接合的模具的开槽表面，其中所述凹槽具有足够的尺寸以提供基本上均匀的模头键合，但没有大到使得到 底层基材。 一种用于在基板和模具之间形成结合的方法，包括：提供基板和模具，其中所述基板具有形成在表面区域中的槽，用于接受用于结合的模具并且具有足够的金属化以与所述基板和模具形成共晶键 在其上具有金金属化的模具; 以及在所述基底和所述模具之间形成共晶粘结，包括加热所述基底，将所述基底的所述金属化带槽的表面接触所述金属模的金金属化表面，通过在保持接触的同时前后移动所述冲模将所述冲模擦洗到所述基底上， 并冷却基板和模具。 一种微电子结构，包括基板和模具，其中所述基板在适于与所述模具结合的表面上具有凹槽，并且其中在所述基板和所述模具之间形成结合。

公开(公告)号：US20240347493A1

公开(公告)日：2024-10-17

申请号：US18383512

申请日：2023-10-25

申请人： CHIPBOND TECHNOLOGY CORPORATION

发明人： Wei-Hsin Wu ,  Ku-Pang Chang ,  Chun-Chia Yeh

IPC分类号： H01L23/00 ,  H01L23/498 ,  H05K1/11

CPC分类号： H01L24/16 ,  H01L23/49838 ,  H01L24/08 ,  H05K1/118 ,  H01L2224/0801 ,  H01L2224/08225 ,  H01L2224/16012 ,  H01L2224/16225 ,  H01L2924/3511 ,  H01L2924/384

摘要： A semiconductor package includes a flexible circuit board and a chip which includes a first bump group and a second bump group. First bumps of the first bump group and second bumps of the second bump group are provided to be bonded to leads on the flexible circuit board. The second bumps are designed to be longer than the first bumps in length so as to increase bonding strength of the second bumps to the leads, prevent the leads from being shifted and separated from the first and second bumps and prevent lead bonding misalignment.

公开(公告)号：US20240347492A1

公开(公告)日：2024-10-17

申请号：US18343490

申请日：2023-06-28

申请人： Mitsubishi Electric Corporation

发明人： Shin CHAKI

IPC分类号： H01L23/00 ,  H01L21/66 ,  H01L23/29 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498

CPC分类号： H01L24/16 ,  H01L22/32 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16238 ,  H01L2224/32221 ,  H01L2224/73253 ,  H01L2924/384

摘要： A semiconductor device includes: a multi-layer substrate; and a semiconductor chip mounted on the multi-layer substrate by flip-chip mounting and having an internal circuit, wherein plural pads are formed on a front surface of the semiconductor chip, plural pillars are respectively formed on the plural pads, plural upper-surface electrodes are formed on an upper surface of the multi-layer substrate, plural lower-surface electrodes are formed on a lower surface of the multi-layer substrate and are respectively connected with the plural upper-surface electrodes via through holes, the plural pillars are joined to the plural upper-surface electrodes by solder, the plural pads include an electrode pad connected with the internal circuit and plural inspection pads formed in at least three parts in four corners on the front surface of the semiconductor chip and not connected with the internal circuit, and a line connects the adjacent inspection pads with each other.

公开(公告)号：US20240088271A1

公开(公告)日：2024-03-14

申请号：US18491353

申请日：2023-10-20

申请人： Murata Manufacturing Co., Ltd.

发明人： Atsushi KUROKAWA ,  Mari SAJI

IPC分类号： H01L29/73 ,  H01L23/00 ,  H01L29/08 ,  H01L29/417 ,  H01L29/737

CPC分类号： H01L29/7317 ,  H01L24/16 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/737 ,  H01L2224/1601 ,  H01L2224/16155 ,  H01L2924/014 ,  H01L2924/384

摘要： A semiconductor device has a semiconductor substrate, at least one first transistor that has a mesa structure including one or more semiconductor layers, a first bump that overlaps the first transistor and extends in a first direction, and a second bump, in which the mesa structure has a first end portion on one end side in a second direction and a second end portion on the other end side in the second direction. The opening has a first opening end portion and a second opening end portion that are adjacent in the second direction. In plan view, the first opening end portion is closer to the second bump than the second opening end portion and the first end portion and the second end portion of the mesa structure are disposed between the first opening end portion and the second opening end portion.

公开(公告)号：US20240021558A1

公开(公告)日：2024-01-18

申请号：US18331150

申请日：2023-06-07

申请人： Powertech Technology Inc.

发明人： Shang-Yu CHANG-CHIEN

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16

CPC分类号： H01L24/17 ,  H01L21/561 ,  H01L21/4853 ,  H01L23/3107 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L25/165 ,  H01L24/09 ,  H01L2224/1703 ,  H01L2224/17179 ,  H01L2224/17136 ,  H01L2224/17104 ,  H01L2224/16054 ,  H01L2224/16055 ,  H01L2224/16265 ,  H01L2224/32268 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/96 ,  H01L2224/95001 ,  H01L2225/10 ,  H01L2224/09179 ,  H01L2924/384

摘要： A chip structure has a chip body having a plurality of pads, a plurality of metal bumps respectively formed on the pads, and a patterned bump directly formed on the chip body. The patterned bump has at least two different upper and lower plane patterns. A top surface of each of the metal bumps is higher than a height position on which the upper plane pattern is. When the chip structure is ground to the height position, the ground tops of the metal bumps and the upper plane pattern are flush. Therefore, detecting whether the upper plane pattern is exposed determines whether all the metal bumps are exposed and flush to each other to avoid insufficient grinding depth or over-ground.

公开(公告)号：US20180358324A1

公开(公告)日：2018-12-13

申请号：US16106133

申请日：2018-08-21

申请人： Micron Technology, Inc.

发明人： Young Do Kweon ,  Tongbi Jiang

IPC分类号： H01L23/00 ,  H01L21/48

CPC分类号： H01L24/742 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/566 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/11 ,  H01L24/12 ,  H01L24/14 ,  H01L24/16 ,  H01L24/18 ,  H01L24/81 ,  H01L24/94 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54486 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/11013 ,  H01L2224/11015 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/7598 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/384 ,  H01L2924/00

摘要： Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

公开(公告)号：US10083931B2

公开(公告)日：2018-09-25

申请号：US14964096

申请日：2015-12-09

申请人： Micron Technology, Inc.

发明人： Young Do Kweon ,  Tongbi Jiang

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L23/544 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

CPC分类号： H01L24/742 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/566 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/11 ,  H01L24/12 ,  H01L24/14 ,  H01L24/16 ,  H01L24/18 ,  H01L24/81 ,  H01L24/94 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54486 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/11013 ,  H01L2224/11015 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/7598 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/384 ,  H01L2924/00

摘要： Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

公开(公告)号：US09897444B2

公开(公告)日：2018-02-20

申请号：US14580370

申请日：2014-12-23

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Elaine Cyr ,  Dominique L. Demers ,  Paul F. Fortier ,  Alexander Janta-Polczynski

IPC分类号： G01B5/18 ,  G01B21/16 ,  H01L23/00 ,  G01B11/06 ,  G01B11/14

CPC分类号： G01B21/16 ,  G01B11/0608 ,  G01B11/14 ,  G01B2210/56 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/75753 ,  H01L2224/75901 ,  H01L2224/81908 ,  H01L2924/14 ,  H01L2924/384 ,  H01L2924/014 ,  H01L2924/00014

摘要： Systems and methods are provided for obtaining measurements of an integrated circuit chip and a connected carrier to obtain the measurements of the interconnect heights. More specifically, a method is provided that includes defining a top best fit reference plane and a bottom best fit reference plane, and adjusting the top best fit reference and the bottom best fit reference to be superposed to one another. The method further includes calculating first distances between each height measurement for a first set of points and the adjusted top best fit reference plane, and calculating second distances between each height measurement for a second set of points and the adjusted bottom best fit reference plane. The method further includes calculating height values of a gap or interconnect between the first substrate and the second substrate by subtracting the thickness of the first substrate and the second distances from the first distances.