公开(公告)号：US11742380B2

公开(公告)日：2023-08-29

申请号：US17714740

申请日：2022-04-06

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Haitao Liu ,  Matthew J. King

IPC: G11C16/16 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L29/0638 ,  G11C16/0483 ,  G11C16/16 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of the topmost select gate transistors to strings of memory cells upon application of a voltage to the gates of the topmost select gate transistors. This electric field can be provided by using a dissected plug as a contact to the channel structure of the topmost select gate transistor, where the dissected plug has one or more conductive regions contacting the channel structure and one or more non-conductive regions contacting the channel structure. The dissected plug can be part of a contact between the data line and the channel structure. Additional devices, systems, and methods are discussed.

公开(公告)号：US11733921B2

公开(公告)日：2023-08-22

申请号：US17244060

申请日：2021-04-29

Applicant: SK hynix Inc.

Inventor： Won Jae Choi ,  Jea Won Choi

IPC: G11C16/24 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0683 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C2216/22

Abstract: The present technology relates to a memory device. A memory device according to the present technology may include a plurality of planes, individual operation controllers configured to respectively control read operations on the plurality of planes, a common operation controller configured to control a program operation or an erase operation on any one of the plurality of planes, a command decoder configured to provide a read command among the plurality of commands to an individual operation controller that controls a plane that is indicated by an address that corresponds to the read command among the individual operation controllers, and configured to provide a program command or an erase command among the plurality of commands to the common operation controller, and a peripheral circuit configured to generate operation voltages that are used for the read operations, the program operation, and the erase operation.

公开(公告)号：US11733873B2

公开(公告)日：2023-08-22

申请号：US15829590

申请日：2017-12-01

Applicant: Micron Technology, Inc.

Inventor： Zoltan Szubbocsev

IPC: G06F3/06 ,  G06F12/10 ,  G11C11/00 ,  G11C16/34 ,  G11C11/56 ,  G11C16/16 ,  G06F12/02

CPC classification number: G06F3/0616 ,  G06F3/0649 ,  G06F3/0688 ,  G06F12/10 ,  G11C11/005 ,  G11C16/3486 ,  G11C16/3495 ,  G06F2212/2022 ,  G06F2212/657 ,  G11C11/5635 ,  G11C16/16

Abstract: A computer storage device having: a host interface; a controller; non-volatile storage media having memory units of different types and having different program erase budgets; and firmware. The firmware instructs the controller to: generate an address map mapping logical addresses to physical addresses of the memory units the different types; and adjust the address map based at least in part on the program erase budgets to level wear across the memory units of the different types.

公开(公告)号：US20230253036A1

公开(公告)日：2023-08-10

申请号：US18109390

申请日：2023-02-14

Applicant: Mosaid Technologies Incorporated

Inventor： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

IPC: G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/06

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US11715726B2

公开(公告)日：2023-08-01

申请号：US17555383

申请日：2021-12-18

Applicant: SK hynix Inc.

Inventor： Sung Lae Oh ,  Ki Soo Kim ,  Sang Woo Park ,  Dong Hyuk Chae

IPC: G11C16/00 ,  H01L25/065 ,  H01L23/00 ,  G11C16/10 ,  G11C16/16 ,  G11C16/04 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L25/0657 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H01L24/08 ,  H10B43/27 ,  H10B43/40 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes: a first wafer including a first substrate, a plurality of first electrode layers and a plurality of first interlayer dielectric layers alternately stacked along first vertical channels projecting in a vertical direction on a top surface of the first substrate, and a dielectric stack comprising a plurality of dielectric layers and the plurality of first interlayer dielectric layers alternately stacked on the top surface of the first substrate; and a second wafer disposed on the first wafer, and including a second substrate, and a plurality of second electrode layers that are alternately stacked with a plurality of second interlayer dielectric layers along second vertical channels projecting in the vertical direction on a bottom surface of the second substrate and have pad parts overlapping with the dielectric stack in the vertical direction.

公开(公告)号：US11715533B2

公开(公告)日：2023-08-01

申请号：US17377857

申请日：2021-07-16

Applicant: KIOXIA CORPORATION

Inventor： Hiroshi Maejima

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/32 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3459

Abstract: A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.

公开(公告)号：US20230229887A1

公开(公告)日：2023-07-20

申请号：US18123918

申请日：2023-03-20

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh BAYAT ,  Xinjie GUO ,  Dmitri STRUKOV ,  Nhan DO ,  Hieu Van TRAN ,  Vipin TIWARI ,  Mark REITEN

IPC: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/34 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/06

CPC classification number: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/3436 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688

Abstract: Numerous examples are disclosed for an output block coupled to a non-volatile memory array in a neural network and associated methods. In one example, a circuit for converting a current in a neural network into an output voltage comprises a non-volatile memory cell comprises a word line terminal, a bit line terminal, and a source line terminal, wherein the bit line terminal receives the current; and a switch for selectively coupling the word line terminal to the bit line terminal; wherein when the switch is closed, the current flows into the non-volatile memory cell and the output voltage is provided on the bit line terminal.

公开(公告)号：US20230223082A1

公开(公告)日：2023-07-13

申请号：US17955733

申请日：2022-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoung-Ho SON ,  Doo-Yeun JUNG ,  Sung-Kwan JUNG

IPC: G11C16/08 ,  G11C16/16 ,  G11C29/12

CPC classification number: G11C16/08 ,  G11C16/16 ,  G11C29/12 ,  G11C16/0483

Abstract: An operating method of a memory device includes: acquiring an address of a first bad word line, the first bad word line included in a plurality of word lines of the memory device; detecting whether word lines adjacent to the first bad word line are bad based on the address of the first bad word line, the word lines adjacent to the first bad word line included in the plurality of word lines; designating a first word line among the word lines adjacent to the first bad word line as a prohibited word line, the first word line being detected as a second bad word line; and sending first data via a second word line among the word lines adjacent to the first bad word line, the second word line being detected as a normal word line.

公开(公告)号：US11699490B2

公开(公告)日：2023-07-11

申请号：US17220218

申请日：2021-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soyeong Gwak ,  Raeyoung Lee ,  Jinkyu Kang ,  Sejun Park ,  Changhwan Shin ,  Jaeduk Lee ,  Woojae Jang

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/26 ,  G11C7/10 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/16 ,  G11C7/106 ,  G11C7/1087 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/349

Abstract: An operating method of a storage device includes reading a wear-out pattern of a memory block when a controller determines the memory block is a re-use memory block of a non-volatile memory device; selecting an operation mode corresponding to the read wear-out pattern using the controller; and transmitting the selected operation mode to the non-volatile memory device using the controller.

公开(公告)号：US20230207644A1

公开(公告)日：2023-06-29

申请号：US17968037

申请日：2022-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Joo JEON ,  Byung Joo Go ,  Hee-Sung Kam ,  Su Jin Park

IPC: H01L29/417 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  G11C16/04 ,  G11C16/26 ,  G11C16/16

CPC classification number: H01L29/41775 ,  G11C16/16 ,  G11C16/26 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573

Abstract: A semiconductor device includes: a substrate includes an active area; a gate structure intersecting the active area; a source/drain area disposed on the active area, a lower contact disposed on the source/drain area or the gate structure; an upper contact disposed on the lower contact; and a plurality of conductive lines disposed on the upper contact, wherein the plurality of conductive lines extend in a first direction parallel to an upper surface of the substrate, wherein the plurality of conductive lines includes a first conductive line disposed on the upper contact, wherein a size in the first direction of the lower contact is smaller than a size in the first direction of the upper contact, wherein a size in a second direction of the lower contact is greater than a size in the second direction of the upper contact, wherein the second direction intersects the first direction.