公开(公告)号：US09548267B2

公开(公告)日：2017-01-17

申请号：US14712940

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming Hsien Tsai ,  Hsieh-Hung Hsieh ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Sa-Lly Liu ,  Fu-Lung Hsueh

IPC: H01L27/08 ,  H01L23/522 ,  H01L49/02 ,  H01L23/538 ,  H01L23/58 ,  H01L27/06 ,  H01L27/07 ,  H01L23/48 ,  H03F1/26 ,  H03F3/04 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5384 ,  H01L23/585 ,  H01L23/645 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/0705 ,  H01L27/092 ,  H01L28/10 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2924/0002 ,  H03F1/26 ,  H03F3/04 ,  H03F2200/294 ,  H03F2200/372 ,  H01L2924/00

Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.

Abstract translation: 三维（3D）电路包括包括半导体衬底的第一层，与第一层相邻设置的第二层，包括电感元件部分的三维电感器，电感元件部分包括从第一层延伸到 第二层的介电层。 3D电路包括围绕导电通孔的至少一部分的接地屏蔽。 在一些实施例中，接地屏蔽包括中空圆柱形笼。 在一些实施例中，3D电路是低噪声放大器。

公开(公告)号：US20170005056A1

公开(公告)日：2017-01-05

申请号：US15266752

申请日：2016-09-15

Applicant: Apple Inc.

Inventor： Anthony Fai ,  Evan R. Boyle ,  Zhiping Yang ,  Zhonghua Wu

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/552 ,  H01L23/60 ,  H01L24/06 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/065 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06151 ,  H01L2224/06177 ,  H01L2224/1405 ,  H01L2224/1414 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Abstract translation: 为层叠半导体存储器封装提供了系统和方法。 每个封装可以包括集成电路（“IC”）封装基板，能够通过两个通道将数据传输到堆叠在封装内的存储器管芯。 每个通道可以位于IC封装衬底的一侧，并且来自每个通道的信号可以从它们各自的侧面被引导到存储器管芯。

公开(公告)号：US20160379952A1

公开(公告)日：2016-12-29

申请号：US14902504

申请日：2014-07-02

Applicant: ROSENBERGER HOCHFREQUENZTECHNIK GMBH & CO. KG

Inventor： Sean S. Cahill ,  Eric A. Sanjuan

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/66

CPC classification number: H01L24/45 ,  H01L23/367 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2223/6611 ,  H01L2223/6677 ,  H01L2224/05553 ,  H01L2224/45014 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/8592 ,  H01L2224/85935 ,  H01L2224/85939 ,  H01L2225/06506 ,  H01L2225/06537 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/1052 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01Q1/283 ,  H01Q23/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A die interconnect system having a first die with a plurality of connection pads, and a ribbon lead extending from the first die, the ribbon lead having a plurality of metal cores with a core diameter, and a dielectric layer surrounding the metal core with a dielectric thickness, with at least a portion of dielectric being fused between adjacent metal cores along the length of the plurality of metal cores, and an outer metal layer attached to ground.

Abstract translation: 一种芯片互连系统，具有具有多个连接焊盘的第一裸片和从第一裸片延伸的色带引线，所述色带引线具有多个具有芯直径的金属芯，以及围绕所述金属芯的电介质层， 电介质的至少一部分沿着多个金属芯的长度被熔合在相邻的金属芯之间，以及附着在地面上的外部金属层。

公开(公告)号：US09484279B2

公开(公告)日：2016-11-01

申请号：US12792031

申请日：2010-06-02

Applicant: Reza A. Pagaila ,  Flynn Carson ,  Seung Uk Yoon

Inventor： Reza A. Pagaila ,  Flynn Carson ,  Seung Uk Yoon

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/11 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/552 ,  H01L21/4871 ,  H01L21/561 ,  H01L21/568 ,  H01L23/06 ,  H01L23/10 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5286 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/95 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/115 ,  H01L2223/6677 ,  H01L2224/02166 ,  H01L2224/0217 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/73253 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2225/06524 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier. A flat shielding layer is formed over the encapsulant. A channel is formed through the shielding layer and encapsulant down to the interface layer. A conductive material is deposited in the channel and electrically connected to the shielding layer. The interface layer and carrier are removed. An interconnect structure is formed over conductive material, encapsulant, and first die. The conductive material is electrically connected through the interconnect structure to a ground point. The conductive material is singulated to separate the first die. A second semiconductor die can be mounted over the first die such that the shielding layer covers the second die and the conductive material surrounds the second die or the first and second die.

Abstract translation: 半导体器件具有安装在形成在临时载体上的界面层上的多个第一半导体管芯。 密封剂沉积在第一模具和载体上。 在密封剂上形成平坦的屏蔽层。 通过屏蔽层和密封剂形成通道，直到界面层。 导电材料沉积在通道中并电连接到屏蔽层。 界面层和载体被去除。 在导电材料，密封剂和第一模具上形成互连结构。 导电材料通过互连结构电连接到接地点。 将导电材料分开以分离第一模具。 可以将第二半导体管芯安装在第一管芯上，使得屏蔽层覆盖第二管芯，并且导电材料围绕第二管芯或第一和第二管芯。

公开(公告)号：US09455228B2

公开(公告)日：2016-09-27

申请号：US14146895

申请日：2014-01-03

Applicant: Apple Inc.

Inventor： Altan N. Yazar ,  Kiavash Baratzadeh ,  Michael J. Reilly ,  Sean A. Mayo

IPC: H05K9/00 ,  H01L23/552 ,  H05K1/02 ,  H05K3/34 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0243 ,  H05K3/3436 ,  H05K9/0028 ,  H05K2201/0715 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: This is directed to self-shielded components and methods for making the same. A self-shielded component can include an electromagnetic interference (EMI) shield that contains circuitry within a shielded space defined by the EMI shield. Self-shielding can be achieved by interfacing a conformal shield layer to a ground layer disposed on or within a substrate of the self-shielded component. The combination of the conformal shield layer and the around layer can form a boundary of the shielded space that envelops circuitry requiring shielding. This enables the self-shielded component to be mounted to a circuit board without requiring a shield can or other processing to impart EMI shielding. In addition, the self-shielded components include the benefits of EMI shielding while simultaneously decreasing space requirements.

Abstract translation: 这是针对自屏蔽组件和制作相同的方法。 自屏蔽部件可以包括电磁干扰（EMI）屏蔽，其包含由EMI屏蔽限定的屏蔽空间内的电路。 可以通过将保形屏蔽层与设置在自屏蔽部件的基板上或内部的接地层相接合来实现自屏蔽。 共形屏蔽层和周围层的组合可以形成包围需要屏蔽的电路的屏蔽空间的边界。 这使得自屏蔽部件能够安装到电路板，而不需要屏蔽罩或其它处理来施加EMI屏蔽。 此外，自屏蔽组件还包括EMI屏蔽的优点，同时降低了空间要求。

公开(公告)号：US09406621B2

公开(公告)日：2016-08-02

申请号：US12797971

申请日：2010-06-10

Applicant: Allan T. Mitchell ,  Keith Jarreau

Inventor： Allan T. Mitchell ,  Keith Jarreau

IPC: H01L23/552 ,  H01L23/522 ,  B81B7/00 ,  H01L29/786 ,  H01L27/115

CPC classification number: H01L23/552 ,  B81B7/0064 ,  H01L23/5225 ,  H01L27/11517 ,  H01L29/78633 ,  H01L2225/06537 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

Abstract: An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.

Abstract translation: 一种具有非易失性存储单元的集成电路，通过与化学机械处理兼容的屏蔽结构来屏蔽紫外线。 所公开的屏蔽结构包括具有侧面的屋顶结构; 沿着每一侧具有间隔开的接触柱，每个接触柱具有要被屏蔽的紫外线的波长的宽度，并隔开一定距离，该距离也在要被屏蔽的紫外线的波长的数量级上。 接触柱可以设置成多排，并且延伸到扩散区域或多晶硅环或两者。 多行可以彼此对准或相互交错排列。

公开(公告)号：US20160181227A1

公开(公告)日：2016-06-23

申请号：US14577735

申请日：2014-12-19

Applicant: Elwha LLC

Inventor： Douglas C. Burger ,  William Gates ,  Andrew F. Glew ,  Roderick A. Hyde ,  Muriel Y. Ishikawa ,  Jordin T. Kare ,  John L. Manferdelli ,  Thomas M. McWilliams ,  Craig J. Mundie ,  Nathan P. Myhrvold ,  Burton J. Smith ,  Clarence T. Tegreene ,  Thomas A. Weaver ,  Richard T. Witek ,  Lowell L. Wood,, JR. ,  Victoria Y.H. Wood

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/34 ,  H01L43/02 ,  H01L43/08 ,  H01L23/522 ,  H01L23/64

CPC classification number: H01L25/0657 ,  H01L23/34 ,  H01L23/345 ,  H01L23/48 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/645 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A non-contacting inductive interconnect of a three-dimensional integrated circuit includes a first silicon substrate having a first inductive loop. A first layer of high permeability material is deposited on the first silicon substrate that has the first inductive loop forming a first high permeability structure. The circuit further includes a second silicon substrate having a second inductive loop. A magnetic coupling is formed between the first inductive loop and the second inductive loop. The first high permeability structure can enhance the magnetic coupling between the first inductive loop and the second inductive loop. In some embodiments, a second layer of the high permeability material is deposited on the second silicon substrate that has the second inductive loop forming a second high permeability structure. The first high permeability structure and the second high permeability structure can form a magnetic circuit coupling the first inductive loop and the second inductive loop.

Abstract translation: 三维集成电路的非接触感应互连包括具有第一感应环路的第一硅衬底。 第一层高磁导率材料沉积在具有形成第一高导磁率结构的第一感应回路的第一硅衬底上。 该电路还包括具有第二感应回路的第二硅衬底。 在第一感应回路和第二感应回路之间形成磁耦合。 第一高导磁率结构可以增强第一感应回路和第二感应回路之间的磁耦合。 在一些实施例中，高导磁率材料的第二层沉积在具有形成第二高导磁率结构的第二感应环的第二硅衬底上。 第一高磁导率结构和第二高磁导率结构可以形成耦合第一感应回路和第二感应回路的磁路。

公开(公告)号：US09355892B2

公开(公告)日：2016-05-31

申请号：US14021923

申请日：2013-09-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Nan Shih

IPC: H01L29/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L21/76805 ,  H01L23/481 ,  H01L23/5223 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/11 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure.

Abstract translation: 集成电路结构包括包括第一层和第二层的双层管芯，并结合到第一层。 第一层包括第一衬底，其包括半导体材料，在第一衬底的表面处的有源器件，以及在第一衬底上的第一互连结构，其中第一层在其中没有被动器件。 第二层包括结合到第一互连结构并与第一互连结构接触的第二衬底，以及在第二衬底上的第二互连结构，其中第二互连结构中的金属线电耦合到第一互连结构。 第二层还包括穿过第二衬底的多个通孔，其中多个通孔位于第一互连结构的顶部金属层中的金属焊盘上，以及第二互连结构中的无源器件。

公开(公告)号：US09318474B2

公开(公告)日：2016-04-19

申请号：US14192145

申请日：2014-02-27

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Yizhang Yang ,  Mengzhi Pang

IPC: H01L23/34 ,  H01L25/16 ,  H01L25/00 ,  H01L23/00 ,  H01L23/36 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L25/165 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08225 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81894 ,  H01L2224/83894 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649

Abstract: In some embodiments, a semiconductor device package assembly may include a first substrate. The semiconductor device package assembly may include a first die electrically connected to the first substrate such that the first die is directly bonded to the first substrate. The semiconductor device package assembly may include a second substrate directly bonded to a surface of the first die. The semiconductor device package assembly may include an electronic memory module. The electronic memory module may be directly bonded to the second substrate. The semiconductor device package assembly may include a thermally conductive material directly applied to the electronic memory module. The semiconductor device package assembly may include a heat spreader directly bonded to the thermally conductive material. The heat spreader may function to transfer heat from the first die and the electronic memory module through the heat spreader from the first side to the second side.

Abstract translation: 在一些实施例中，半导体器件封装组件可以包括第一衬底。 半导体器件封装组件可以包括电连接到第一衬底的第一裸片，使得第一裸片直接结合到第一衬底。 半导体器件封装组件可以包括直接接合到第一管芯的表面的第二衬底。 半导体器件封装组件可以包括电子存储器模块。 电子存储器模块可以直接结合到第二衬底。 半导体器件封装组件可以包括直接施加到电子存储器模块的导热材料。 半导体器件封装组件可以包括直接结合到导热材料的散热器。 散热器可以起到将热量从第一模具和电子存储器模块通过散热器从第一侧传递到第二侧的功能。

公开(公告)号：US09275976B2

公开(公告)日：2016-03-01

申请号：US13405207

申请日：2012-02-24

Applicant: Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

Inventor： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC: H01L23/552 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/552 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06572 ,  H01L2225/06589

Abstract: There are disclosed herein various implementations of a system-in-package with integrated socket. In one such implementation, the system-in-package includes a first active die having a first plurality of electrical connectors on a top surface of the first active die, an interposer situated over the first active die, and a second active die having a second plurality of electrical connectors on a bottom surface of the second active die. The interposer is configured to selectively couple at least one of the first plurality of electrical connectors to at least one of the second plurality of electrical connectors. In addition, a socket encloses the first and second active dies and the interposer, the socket being electrically coupled to at least one of the first active die, the second active die, and the interposer.

Abstract translation: 这里公开了具有集成插座的系统级封装的各种实施方式。 在一个这样的实现中，系统级封装包括第一有源裸片，其具有在第一有源裸片的顶表面上的第一多个电连接器，位于第一有源裸片上的中介层，以及具有第二激活裸片的第二激活裸片 多个电连接器在第二有源管芯的底表面上。 插入器被配置为选择性地将第一多个电连接器中的至少一个耦合到第二多个电连接器中的至少一个。 此外，插座包围第一和第二有源裸片和插入器，插座电耦合到第一有源裸片，第二激活裸片和插入器中的至少一个。