公开(公告)号：US20120313180A1

公开(公告)日：2012-12-13

申请号：US13569730

申请日：2012-08-08

Applicant: Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

Inventor： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

IPC: H01L21/8239 ,  H01L27/088

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L27/11226 ,  H01L29/4983 ,  H01L29/861

Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

Abstract translation: 在本发明的实施例中，公开了一种非易失性反熔丝存储器单元。 存储单元由可编程的n沟道二极管连接晶体管组成。 晶体管的多晶硅栅极具有两部分。 一部分掺杂比第二部分更高。 晶体管还具有源的两部分，其中源的一部分被掺杂得比第二部分更高。 物理上更接近源极的栅极的部分比多晶硅栅极的其他部分更轻掺杂。 物理上更靠近聚硅氧烷栅极的轻掺杂部分的源的部分相对于源的另一部分被轻掺杂。 当晶体管被编程时，在重掺杂的聚硅氧烷栅极的部分中绝大多数情况下会发生破裂。

公开(公告)号：US20100032744A1

公开(公告)日：2010-02-11

申请号：US12537086

申请日：2009-08-06

Applicant: Jozef C. Mitros ,  Keith Jarreau ,  Pinghai Hao

Inventor： Jozef C. Mitros ,  Keith Jarreau ,  Pinghai Hao

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/7883 ,  H01L21/28273 ,  H01L29/0692 ,  H01L29/42324 ,  H01L29/66825

Abstract: A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.

Abstract translation: 单个多晶EEPROM单元，其中读取晶体管集成在控制栅阱或擦除栅极中。 控制栅极与擦除栅极阱的横向分离可以减小到在编程和擦除操作期间遇到的耗尽区的宽度。 形成单个多晶硅EEPROM单元的方法，其中读取晶体管集成在控制栅极阱或擦除栅极阱中。

公开(公告)号：US20110303959A1

公开(公告)日：2011-12-15

申请号：US12797971

申请日：2010-06-10

Applicant: Allan T. Mitchell ,  Keith Jarreau

Inventor： Allan T. Mitchell ,  Keith Jarreau

IPC: H01L29/788 ,  H01L21/3205

CPC classification number: H01L23/552 ,  B81B7/0064 ,  H01L23/5225 ,  H01L27/11517 ,  H01L29/78633 ,  H01L2225/06537 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

Abstract: An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.

Abstract translation: 一种具有非易失性存储单元的集成电路，通过与化学机械处理兼容的屏蔽结构来屏蔽紫外线。 所公开的屏蔽结构包括具有侧面的屋顶结构; 沿着每一侧具有间隔开的接触柱，每个接触柱具有要被屏蔽的紫外线的波长的宽度，并隔开一定距离，该距离也在要被屏蔽的紫外线的波长的数量级上。 接触柱可以设置成多排，并且延伸到扩散区域或多晶硅环或两者。 多行可以彼此对准或相互交错排列。

公开(公告)号：US08946805B2

公开(公告)日：2015-02-03

申请号：US12537086

申请日：2009-08-06

Applicant: Jozef C. Mitros ,  Keith Jarreau ,  Pinghai Hao

Inventor： Jozef C. Mitros ,  Keith Jarreau ,  Pinghai Hao

IPC: H01L29/788 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/7883 ,  H01L21/28273 ,  H01L29/0692 ,  H01L29/42324 ,  H01L29/66825

Abstract: A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.

Abstract translation: 单个多晶EEPROM单元，其中读取晶体管集成在控制栅阱或擦除栅极中。 控制栅极与擦除栅极阱的横向分离可以减小到在编程和擦除操作期间遇到的耗尽区的宽度。 形成单个多晶硅EEPROM单元的方法，其中读取晶体管集成在控制栅极阱或擦除栅极阱中。

公开(公告)号：US08748235B2

公开(公告)日：2014-06-10

申请号：US13569730

申请日：2012-08-08

Applicant: Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

Inventor： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

IPC: H01L21/336

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L27/11226 ,  H01L29/4983 ,  H01L29/861

Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

Abstract translation: 在本发明的实施例中，公开了一种非易失性反熔丝存储器单元。 存储单元由可编程的n沟道二极管连接晶体管组成。 晶体管的多晶硅栅极具有两部分。 一部分掺杂比第二部分更高。 晶体管还具有源的两部分，其中源的一部分被掺杂得比第二部分更高。 物理上更接近源极的栅极的部分比多晶硅栅极的其他部分更轻掺杂。 物理上更靠近聚硅氧烷栅极的轻掺杂部分的源的部分相对于源的另一部分被轻掺杂。 当晶体管被编程时，在重掺杂的聚硅氧烷栅极的部分中绝大多数情况下会发生破裂。

公开(公告)号：US08258586B1

公开(公告)日：2012-09-04

申请号：US13045725

申请日：2011-03-11

Applicant: Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

Inventor： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

IPC: H01L27/115

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L27/11226 ,  H01L29/4983 ,  H01L29/861

Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

Abstract translation: 在本发明的实施例中，公开了一种非易失性反熔丝存储器单元。 存储单元由可编程的n沟道二极管连接晶体管组成。 晶体管的多晶硅栅极具有两部分。 一部分掺杂比第二部分更高。 晶体管还具有源的两部分，其中源的一部分被掺杂得比第二部分更高。 物理上更接近源极的栅极的部分比多晶硅栅极的其他部分更轻掺杂。 物理上更靠近聚硅氧烷栅极的轻掺杂部分的源的部分相对于源的另一部分被轻掺杂。 当晶体管被编程时，在重掺杂的聚硅氧烷栅极的部分中绝大多数情况下会发生破裂。

公开(公告)号：US09406621B2

公开(公告)日：2016-08-02

申请号：US12797971

申请日：2010-06-10

Applicant: Allan T. Mitchell ,  Keith Jarreau

Inventor： Allan T. Mitchell ,  Keith Jarreau

IPC: H01L23/552 ,  H01L23/522 ,  B81B7/00 ,  H01L29/786 ,  H01L27/115

CPC classification number: H01L23/552 ,  B81B7/0064 ,  H01L23/5225 ,  H01L27/11517 ,  H01L29/78633 ,  H01L2225/06537 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

Abstract: An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.

Abstract translation: 一种具有非易失性存储单元的集成电路，通过与化学机械处理兼容的屏蔽结构来屏蔽紫外线。 所公开的屏蔽结构包括具有侧面的屋顶结构; 沿着每一侧具有间隔开的接触柱，每个接触柱具有要被屏蔽的紫外线的波长的宽度，并隔开一定距离，该距离也在要被屏蔽的紫外线的波长的数量级上。 接触柱可以设置成多排，并且延伸到扩散区域或多晶硅环或两者。 多行可以彼此对准或相互交错排列。

公开(公告)号：US20120228724A1

公开(公告)日：2012-09-13

申请号：US13045725

申请日：2011-03-11

Applicant: Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

Inventor： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

IPC: H01L23/525 ,  H01L21/8239

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L27/11226 ,  H01L29/4983 ,  H01L29/861

Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

Abstract translation: 在本发明的实施例中，公开了一种非易失性反熔丝存储器单元。 存储单元由可编程的n沟道二极管连接晶体管组成。 晶体管的多晶硅栅极具有两部分。 一部分掺杂比第二部分更高。 晶体管还具有源的两部分，其中源的一部分被掺杂得比第二部分更高。 物理上更接近源极的栅极的部分比多晶硅栅极的其他部分更轻掺杂。 物理上更靠近聚硅氧烷栅极的轻掺杂部分的源的部分相对于源的另一部分被轻掺杂。 当晶体管被编程时，在重掺杂的聚硅氧烷栅极的部分中绝大多数情况下会发生破裂。