公开(公告)号：US06806541B2

公开(公告)日：2004-10-19

申请号：US10791172

申请日：2004-03-01

申请人： Lily X. Springer ,  Binghua Hu ,  Chin-Yu Tsai ,  Jozef C. Mitros

发明人： Lily X. Springer ,  Binghua Hu ,  Chin-Yu Tsai ,  Jozef C. Mitros

IPC分类号： H01L2976

CPC分类号： H01L21/76216

摘要： An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.

公开(公告)号：US07919368B2

公开(公告)日：2011-04-05

申请号：US12474444

申请日：2009-05-29

申请人： Xiaoju Wu ,  Jozef C. Mitros

发明人： Xiaoju Wu ,  Jozef C. Mitros

IPC分类号： H01L21/8244

CPC分类号： G11C16/10 ,  G11C11/34 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558

摘要： Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.

摘要翻译： 集成电路中的电可擦除可编程“只读”存储器（EEPROM）单元，由单个多晶硅级形成。 EEPROM单元由耦合电容器和组合读取晶体管和隧道电容器组成。 耦合电容器的电容远大于隧道电容器的电容。 在一个实施例中，场氧化物隔离结构将装置彼此隔离; 在读取晶体管的源极处的轻掺杂区域提高了击穿电压性能。 在另一个实施例中，沟槽隔离结构和掩埋氧化物层围绕形成耦合电容器和组合读取晶体管和隧道电容器的阱区域。

公开(公告)号：US20100032744A1

公开(公告)日：2010-02-11

申请号：US12537086

申请日：2009-08-06

申请人： Jozef C. Mitros ,  Keith Jarreau ,  Pinghai Hao

发明人： Jozef C. Mitros ,  Keith Jarreau ,  Pinghai Hao

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L29/0692 ,  H01L29/42324 ,  H01L29/66825

摘要： A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.

摘要翻译： 单个多晶EEPROM单元，其中读取晶体管集成在控制栅阱或擦除栅极中。 控制栅极与擦除栅极阱的横向分离可以减小到在编程和擦除操作期间遇到的耗尽区的宽度。 形成单个多晶硅EEPROM单元的方法，其中读取晶体管集成在控制栅极阱或擦除栅极阱中。

公开(公告)号：US06734491B1

公开(公告)日：2004-05-11

申请号：US10331705

申请日：2002-12-30

申请人： Jozef C. Mitros ,  Imran Khan ,  William Nehrer ,  Lou Hutter ,  Dirk Preikszat

发明人： Jozef C. Mitros ,  Imran Khan ,  William Nehrer ,  Lou Hutter ,  Dirk Preikszat

IPC分类号： H01L29788

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor device (200) comprising a semiconductor substrate (210) having source and drain regions (530, 540) located in the semiconductor substrate (210) and having similar doping profiles, wherein a channel region (550) extends from the source region (530) to the drain region (540). The semiconductor device (200) also comprises a dielectric layer (230) located over the source and drain regions (530, 540), the dielectric layer (230) having first and second thicknesses (T1, T2) wherein the second thickness (T2) is substantially less than the first thickness (T1) and is partially located over the channel region (550). The semiconductor device (200) also comprises a gate (510) located over the dielectric layer (230) wherein the second thickness (T2) is located between an end (515) of the gate (510) and one of the source and drain regions (530, 540).

公开(公告)号：US06548874B1

公开(公告)日：2003-04-15

申请号：US09669391

申请日：2000-09-26

申请人： Alec Morton ,  Taylor Efland ,  Chin-yu Tsai ,  Jozef C. Mitros ,  Dan M. Mosher ,  Sam Shichijo ,  Keith Kunz

发明人： Alec Morton ,  Taylor Efland ,  Chin-yu Tsai ,  Jozef C. Mitros ,  Dan M. Mosher ,  Sam Shichijo ,  Keith Kunz

IPC分类号： H01L2976

CPC分类号： H01L27/092 ,  H01L29/0653 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

摘要： An intergrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS p-well region (70) in a silicon substrate (10). Transistor source regions (50), (140) and drain regions (55), (145) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions (70), (80) serve as the drain extension regions of the transistor.

摘要翻译： 用于亚微米CMOS工艺的集成电路漏极延伸晶体管。 在硅衬底（10）中的CMOS n阱区（80）和CMOS p阱区（70）上形成晶体管栅极（40）。 晶体管源极区域（50），（140）和漏极区域（55），（145）形成在各种CMOS阱区域中以形成漏极延伸晶体管，其中CMOS阱区域（70），（80）用作漏极延伸 晶体管的区域。

公开(公告)号：US08946805B2

公开(公告)日：2015-02-03

申请号：US12537086

申请日：2009-08-06

申请人： Jozef C. Mitros ,  Keith Jarreau ,  Pinghai Hao

发明人： Jozef C. Mitros ,  Keith Jarreau ,  Pinghai Hao

IPC分类号： H01L29/788 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L29/0692 ,  H01L29/42324 ,  H01L29/66825

摘要： A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.

摘要翻译： 单个多晶EEPROM单元，其中读取晶体管集成在控制栅阱或擦除栅极中。 控制栅极与擦除栅极阱的横向分离可以减小到在编程和擦除操作期间遇到的耗尽区的宽度。 形成单个多晶硅EEPROM单元的方法，其中读取晶体管集成在控制栅极阱或擦除栅极阱中。

公开(公告)号：US06747308B2

公开(公告)日：2004-06-08

申请号：US10334319

申请日：2002-12-30

申请人： Jozef C. Mitros ,  Lily Springer ,  Roland Bucksch

发明人： Jozef C. Mitros ,  Lily Springer ,  Roland Bucksch

IPC分类号： H01L29788

CPC分类号： H01L29/7885 ,  G11C2216/10 ,  H01L27/115 ,  H01L29/42324

摘要： An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate comprising at least one polysilicon finger (112A-112E) operatively coupling the source region (122) and drain region (120) and a control gate comprising at least one of the polysilicon fingers (112A-112E) capacitively coupled to the floating gate. The EEPROM (100) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.

摘要翻译： EEPROM（100）包括源区（122），漏区（120）; 和多晶硅层（110）。 多晶硅层（110）包括浮动栅极，其包括可操作地耦合源极区域（122）和漏极区域（120）的至少一个多晶硅指状物（112A-112E）和包括至少一个多晶硅指状物（112A- 112E）电容耦合到浮动栅极。 与现有技术的EEPROM相比，EEPROM（100）具有大大减小的面积，因为消除了n阱区域。

公开(公告)号：US06730569B2

公开(公告)日：2004-05-04

申请号：US10001432

申请日：2001-10-25

申请人： Lily X. Springer ,  Binghua Hu ,  Chin-Yu Tsai ,  Jozef C. Mitros

发明人： Lily X. Springer ,  Binghua Hu ,  Chin-Yu Tsai ,  Jozef C. Mitros

IPC分类号： H01L21336

CPC分类号： H01L21/76216

摘要： An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.

公开(公告)号：US07279738B2

公开(公告)日：2007-10-09

申请号：US11145460

申请日：2005-06-02

申请人： Imran M. Khan ,  Louis N. Hutter ,  James (Bob) Todd ,  Jozef C. Mitros ,  William E. Nehrer

发明人： Imran M. Khan ,  Louis N. Hutter ,  James (Bob) Todd ,  Jozef C. Mitros ,  William E. Nehrer

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273

摘要： A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成氧化物层。 多晶硅层从氧化物层向外设置，其中多晶硅层形成浮栅。 PSG层从多晶硅层向外设置并平坦化。 该器件被图形蚀刻以形成电容器通道，其中电容器通道基本上设置在由多晶硅层形成的浮置栅极的上方。 在从多晶硅层向外设置的电容器通道中形成介电层。 形成可操作以充分充电电容器通道的钨插头。

公开(公告)号：US06930005B2

公开(公告)日：2005-08-16

申请号：US10725642

申请日：2003-12-02

申请人： Taylor R. Efland ,  Jozef C. Mitros ,  Imran Khan

发明人： Taylor R. Efland ,  Jozef C. Mitros ,  Imran Khan

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage. The method provides a first well (502) of a first conductivity type, operable as the extension of the transistor drain (501) of the first conductivity type; portions of the well are covered by a first insulator (503) having a first thickness. A second well (504) of the opposite conductivity type is intended to contain the transistor source (506) of the first conductivity type; portions of the second well are covered by a second insulator (507) thinner than the first insulator. The first and second wells form a junction (505) that terminates at the second insulator (530a, 530b). The method deposits a photoresist layer (510) over the wafer, which is patterned by opening a window (510a) that extends from the drain to the junction termination. Next, ions (540) of the first conductivity type are implanted through the window into the first well; these said ions have an energy to limit the penetration depth (541) to the first insulator thickness, and a dose to create a well region (560) of high doping concentration adjacent to the junction termination (530a).

摘要翻译： 一种在保持高晶体管击穿电压的同时降低半导体晶片中的漏极扩展MOS晶体管的漏极电阻的方法。 该方法提供第一导电类型的第一阱（50​​2），其可操作为第一导电类型的晶体管漏极（501）的延伸; 阱的一部分被具有第一厚度的第一绝缘体（503）覆盖。 相反导电类型的第二阱（504）旨在包含第一导电类型的晶体管源（506）; 第二阱的部分被比第一绝缘体薄的第二绝缘体（507）覆盖。 第一和第二阱形成终止于第二绝缘体（530a，530b）的结（505）。 该方法将光致抗蚀剂层（510）沉积在晶片之上，其通过打开从漏极延伸到结终端的窗口（510a）而被图案化。 接下来，通过窗口将第一导电类型的离子（540）注入到第一阱中; 这些所述离子具有将穿透深度（541）限制到第一绝缘体厚度的能量，以及用于产生邻近连接终端（530a）的高掺杂浓度的阱区（560）的剂量。