公开(公告)号：US08946805B2

公开(公告)日：2015-02-03

申请号：US12537086

申请日：2009-08-06

Applicant: Jozef C. Mitros ,  Keith Jarreau ,  Pinghai Hao

Inventor： Jozef C. Mitros ,  Keith Jarreau ,  Pinghai Hao

IPC: H01L29/788 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/7883 ,  H01L21/28273 ,  H01L29/0692 ,  H01L29/42324 ,  H01L29/66825

Abstract: A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.

Abstract translation: 单个多晶EEPROM单元，其中读取晶体管集成在控制栅阱或擦除栅极中。 控制栅极与擦除栅极阱的横向分离可以减小到在编程和擦除操作期间遇到的耗尽区的宽度。 形成单个多晶硅EEPROM单元的方法，其中读取晶体管集成在控制栅极阱或擦除栅极阱中。

公开(公告)号：US20100032744A1

公开(公告)日：2010-02-11

申请号：US12537086

申请日：2009-08-06

Applicant: Jozef C. Mitros ,  Keith Jarreau ,  Pinghai Hao

Inventor： Jozef C. Mitros ,  Keith Jarreau ,  Pinghai Hao

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/7883 ,  H01L21/28273 ,  H01L29/0692 ,  H01L29/42324 ,  H01L29/66825

Abstract: A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.

Abstract translation: 单个多晶EEPROM单元，其中读取晶体管集成在控制栅阱或擦除栅极中。 控制栅极与擦除栅极阱的横向分离可以减小到在编程和擦除操作期间遇到的耗尽区的宽度。 形成单个多晶硅EEPROM单元的方法，其中读取晶体管集成在控制栅极阱或擦除栅极阱中。

公开(公告)号：US08110857B2

公开(公告)日：2012-02-07

申请号：US12713866

申请日：2010-02-26

Applicant: Pinghai Hao ,  Imran Khan ,  Joe Trogolo

Inventor： Pinghai Hao ,  Imran Khan ,  Joe Trogolo

IPC: H01L29/66

CPC classification number: H01L29/8086 ,  H01L29/66901 ,  H01L29/808

Abstract: A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.

Abstract translation: 公开了一种低噪声（1 / f）结场效应晶体管（JFET），其中多个种植体推动晶体管的导电路径离开形成晶体管的层的表面。 以这种方式，导电路径中的电流不太可能受到可能存在于层的表面处的缺陷的干扰，从而减轻（1 / f）噪声。

公开(公告)号：US20100264466A1

公开(公告)日：2010-10-21

申请号：US12825580

申请日：2010-06-29

Applicant: Xiaoju Wu ,  Fan-Chi Frank Hou ,  Pinghai Hao

Inventor： Xiaoju Wu ,  Fan-Chi Frank Hou ,  Pinghai Hao

IPC: H01L27/085 ,  H01L29/80

CPC classification number: H01L29/808 ,  H01L27/098 ,  H01L29/1066 ,  H01L29/66901

Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.

Abstract translation: 本文的公开内容涉及形成低噪声结场效应晶体管（JFET），其中晶体管栅极材料用于形成和电隔离JFET的有源区。 更具体地，有源区域与图案化的栅极电极材料和侧壁间隔物自对准，其有助于期望将有源区域定位在半导体衬底中。 这减轻了在衬底中需要额外的材料以将有源区彼此隔离，其中这些附加材料可以将噪声引入到JFET中。 这也允许一层栅极电介质材料保留在衬底的表面上，其中栅极介电材料层在衬底的表面处提供基本上均匀的界面，其有助于活性区域之间的不受限制的电流流动，从而促进期望的 设备操作。

公开(公告)号：US20100032769A1

公开(公告)日：2010-02-11

申请号：US12538594

申请日：2009-08-10

Applicant: Pinghai Hao ,  Seetharaman Sridhard ,  James Robert Todd

Inventor： Pinghai Hao ,  Seetharaman Sridhard ,  James Robert Todd

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/761 ,  H01L21/331

CPC classification number: H01L21/823481 ,  H01L21/761 ,  H01L21/823493

Abstract: An n-type isolation structure is disclosed which includes an n-type BISO layer in combination with a shallow n-well, in an IC. The n-type BISO layer is formed by implanting n-type dopants into a p-type IC substrate in addition to a conventional n-type buried layer (NBL), prior to growth of a p-type epitaxial layer. The n-type dopants in the BISO implanted layer diffuse upward from the p-type substrate to between one-third and two-thirds of the thickness of the p-type epitaxial layer. The shallow n-type well extends from a top surface of the p-type epitaxial layer to the n-type BISO layer, forming a continuous n-type isolation structure from the top surface of the p-type epitaxial layer to the p-type substrate. The width of the n-type BISO layer may be less than the thickness of the epitaxial layer, and may be used alone or with the NBL to isolate components in the IC.

Abstract translation: 公开了一种在IC中包括与浅n阱结合的n型BISO层的n型隔离结构。 除了常规的n型掩埋层（NBL）之外，在p型外延层生长之前，通过将n型掺杂剂注入到p型IC衬底中来形成n型BISO层。 BISO注入层中的n型掺杂剂从p型衬底向上扩散到p型外延层的厚度的三分之一和三分之二之间。 浅的n型阱从p型外延层的顶表面延伸到n型BISO层，从p型外延层的顶表面到p型外延层形成连续的n型隔离结构 基质。 n型BISO层的宽度可以小于外延层的厚度，并且可以单独使用或与NBL一起使用以隔离IC中的元件。

公开(公告)号：US20080217664A1

公开(公告)日：2008-09-11

申请号：US11715748

申请日：2007-03-08

Applicant: Xiaoju Wu ,  Fan-Chi Frank Hou ,  Pinghai Hao

Inventor： Xiaoju Wu ,  Fan-Chi Frank Hou ,  Pinghai Hao

IPC: H01L29/80 ,  H01L21/335

CPC classification number: H01L29/808 ,  H01L27/098 ,  H01L29/1066 ,  H01L29/66901

Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.

Abstract translation: 本文的公开内容涉及形成低噪声结场效应晶体管（JFET），其中晶体管栅极材料用于形成和电隔离JFET的有源区。 更具体地，有源区域与图案化的栅极电极材料和侧壁间隔物自对准，其有助于期望将有源区域定位在半导体衬底中。 这减轻了在衬底中需要额外的材料以将有源区彼此隔离，其中这些附加材料可以将噪声引入到JFET中。 这也允许一层栅极电介质材料保留在衬底的表面上，其中栅极介电材料层在衬底的表面处提供基本上均匀的界面，其有助于活性区域之间的不受限制的电流流动，从而促进期望的 设备操作。

公开(公告)号：US07244651B2

公开(公告)日：2007-07-17

申请号：US10442524

申请日：2003-05-21

Applicant: Xiaoju Wu ,  Jozef Mitros ,  Pinghai Hao

Inventor： Xiaoju Wu ,  Jozef Mitros ,  Pinghai Hao

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/7838

Abstract: The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be achieved by blocking implantation of the Vtp implant into a channel region of an n-well that substantially underlies a floating gate structure. The Vtp implant can be blocked by providing a mask overlying the surface of the channel region of the n-well during implantation of the Vtp implant.

Abstract translation: 可以减少使用掩埋沟道PMOS技术形成的OTP-EPROM单元的漏电流。 OTP-EPROM的漏电流的减少可以通过将V基质植入物阻挡到基本上位于浮栅结构的n阱的通道区域中来实现。 可以通过在注入植入物期间提供覆盖n阱的沟道区域的表面的掩模来阻止V >tp注入。

公开(公告)号：US20060286741A1

公开(公告)日：2006-12-21

申请号：US11154431

申请日：2005-06-16

Applicant: Shanjen Pan ,  Sameer Pendharkar ,  Pinghai Hao ,  James Todd

Inventor： Shanjen Pan ,  Sameer Pendharkar ,  Pinghai Hao ,  James Todd

IPC: H01L21/8244

CPC classification number: H01L27/0629 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7835

Abstract: Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.

Abstract translation: 制造方法和器件包括在电容器形成期间形成的场板。 在半导体衬底中形成隔离结构。 在半导体衬底中形成阱区。 在阱区域中形成漏极延伸区域。 在器件上形成栅极电介质层。 形成用作栅电极和底电容器板的栅极电极层。 对栅极电极和栅极介电层进行图案化以形成栅极结构。 源区和漏区形成在阱区和漏极延伸区内。 形成也用作电容器电介质的硅化物阻挡层。 在阻挡层上形成场板和顶部电容器板。

公开(公告)号：US20050215018A1

公开(公告)日：2005-09-29

申请号：US11135544

申请日：2005-05-24

Applicant: Pinghai Hao ,  Shanjen Pan ,  Sameer Pendharkar

Inventor： Pinghai Hao ,  Shanjen Pan ,  Sameer Pendharkar

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/338 ,  H01L29/02 ,  H01L29/08 ,  H01L29/78 ,  H01L47/00

CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

Abstract: A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.

Abstract translation: 可以制造晶体管以显示减少的通道热载体效应。 根据本发明的一个方面，制造晶体管结构的方法包括将第一掺杂剂注入到轻掺杂漏极（LDD）区域中以在其中形成浅区域。 第一掺杂剂将衬底渗透至小于LDD结深度的深度。 将第二掺杂剂注入超过LDD结深度的衬底中以形成源/漏区。 第二掺杂剂的注入超过第一掺杂剂的大部分，以限定LDD区域中的浮动环，其缓和了通道热载流子效应。

公开(公告)号：US07989853B2

公开(公告)日：2011-08-02

申请号：US12537589

申请日：2009-08-07

Applicant: Pinghai Hao ,  Sameer Pendharkar ,  Philip L. Hower ,  Marie Denison

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Philip L. Hower ,  Marie Denison

IPC: H01L29/66 ,  H01L21/337

CPC classification number: H01L27/098 ,  H01L29/0649 ,  H01L29/1058 ,  H01L29/402 ,  H01L29/808

Abstract: A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum drain voltage is determined by drain to gate separation and length of a second, horizontal, channel under the gate. Pinch-off voltage and maximum drain potential are dependent on lateral dimensions of the drain and gate wells and may be independently optimized. A method of fabricating the dual channel JFET is also disclosed.

Abstract translation: 公开了可以集成在IC中而不添加工艺步骤的双通道JFET。 夹断电压由源触点附近的第一垂直通道的横向宽度决定。 最大漏极电压由漏极到栅极间隔和栅极下方的第二个水平沟道的长度决定。 夹断电压和最大漏极电位取决于漏极和栅极阱的横向尺寸，并且可以独立优化。 还公开了制造双通道JFET的方法。