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    Half-FinFET semiconductor device and related method
    1.
    发明授权
    Half-FinFET semiconductor device and related method 有权
    半鳍FET半导体器件及相关方法

    公开(公告)号：US09082751B2

    公开(公告)日：2015-07-14

    申请号：US13232737

    申请日：2011-09-14

    Applicant: Xiangdong Chen ,  Wei Xia

    Inventor： Xiangdong Chen ,  Wei Xia

    IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

    CPC classification number: H01L29/4236 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/66787 ,  H01L29/7835 ,  H01L29/785

    Abstract: According to one embodiment, a half-FinFET semiconductor device comprises a gate structure formed over a semiconductor body. The semiconductor body includes a source region comprised of a plurality of fins extending beyond a first side of the gate structure and a continuous drain region adjacent a second side of the gate structure opposite the plurality of fins. The continuous drain region causes the half-FinFET semiconductor device to have a reduced ON-resistance. A method for fabricating a semiconductor device having a half-FinFET structure comprises designating source and drain regions in a semiconductor body, etching the source region to produce a plurality of source fins while masking the drain region during the etching to provide a continuous drain region, thereby resulting in the half-FinFET structure having a reduced ON-resistance.

    Abstract translation: 根据一个实施例，半FinFET半导体器件包括形成在半导体本体上的栅极结构。 半导体本体包括源极区域，该区域包括延伸超过栅极结构的第一侧面的多个鳍片，以及与栅极结构的与多个鳍片相对的第二侧相邻的连续漏极区域。 连续漏极区域使得半FinFET半导体器件具有降低的导通电阻。 一种制造具有半FinFET结构的半导体器件的方法包括：在半导体本体中指定源极和漏极区域，蚀刻源极区域以产生多个源极鳍片，同时在蚀刻期间掩蔽漏极区域以提供连续的漏极区域， 从而导致半FinFET结构具有降低的导通电阻。

    Transistor with reduced channel length variation
    3.
    发明授权
    Transistor with reduced channel length variation 有权
    具有减小通道长度变化的晶体管

    公开(公告)号：US08659081B2

    公开(公告)日：2014-02-25

    申请号：US13613864

    申请日：2012-09-13

    Applicant: Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

    Inventor： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

    IPC: H01L29/78

    CPC classification number: H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

    Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

    Abstract translation: 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

    One-time programmable device having an LDMOS structure
    4.
    发明授权
    One-time programmable device having an LDMOS structure 有权
    具有LDMOS结构的一次性可编程器件

    公开(公告)号：US08493767B2

    公开(公告)日：2013-07-23

    申请号：US13252880

    申请日：2011-10-04

    Applicant: Akira Ito ,  Xiangdong Chen

    Inventor： Akira Ito ,  Xiangdong Chen

    IPC: G11C17/00 ,  H01L23/52

    CPC classification number: H01L29/7816 ,  H01L21/76224 ,  H01L23/5252 ,  H01L27/088 ,  H01L27/11206 ,  H01L27/11226 ,  H01L27/1124 ,  H01L27/11246 ,  H01L27/11266 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.

    Abstract translation: 根据一个实施例，具有横向扩散的金属氧化物半导体（LDMOS）结构的一次性可编程（OTP）器件包括包括通过栅极电极和通过栅极电介质的通过栅极，以及包括编程门 电极和编程栅极电介质。 编程门通过LDMOS结构的漏极扩展区与通过栅极间隔开。 当用于将编程栅极电介质破裂的编程电压施加到编程栅电极时，LDMOS结构为通路提供保护。 一种用于制造这种OTP器件的方法包括形成漏极延伸区域，在漏极延伸区域的第一部分上制造栅极通孔，以及在漏极延伸区域的第二部分上制造编程栅极。

    Programmable fuse
    6.
    发明授权
    Programmable fuse 有权
    可编程保险丝

    公开(公告)号：US08455977B2

    公开(公告)日：2013-06-04

    申请号：US13466986

    申请日：2012-05-08

    Applicant: Wei Xia ,  Xiangdong Chen ,  Akira Ito

    Inventor： Wei Xia ,  Xiangdong Chen ,  Akira Ito

    IPC: H01L29/00

    CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.

    Abstract translation: 根据一个示例性实施例，一种用于形成一次性可编程金属熔丝结构的方法包括在衬底上形成金属熔丝结构，所述金属熔丝结构包括位于介电段和多晶硅段之间的栅极金属段，栅极金属 熔丝形成在栅极金属段的一部分中。 该方法还包括掺杂多晶硅段以便形成由未掺杂多晶硅部分分开的第一和第二掺杂多晶硅部分，其中在一个实施例中，栅极金属熔丝与未掺杂的多晶硅部分基本上共同延伸。 该方法还可以包括在第一掺杂多晶硅部分上形成第一硅化物部分和在第二掺杂多晶硅部分上形成第二硅化物部分，其中第一和第二硅化物部分形成一次性可编程金属熔丝结构的相应端子。

    FINFET DEVICES
    7.
    发明申请
    FINFET DEVICES 有权
    FINFET器件

    公开(公告)号：US20130105942A1

    公开(公告)日：2013-05-02

    申请号：US13287331

    申请日：2011-11-02

    Applicant: Xiangdong Chen ,  Henry Chen ,  Agnes Woo ,  Wei Xia

    Inventor： Xiangdong Chen ,  Henry Chen ,  Agnes Woo ,  Wei Xia

    IPC: H01L29/92 ,  H01L21/02

    CPC classification number: H01L29/785 ,  H01L28/20 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/94

    Abstract: Disclosed are various embodiments of FinFET semiconductor devices. A pair of matched capacitors can be formed that share a common source, drain and/or channel. Accordingly, the capacitance characteristics of each capacitor can be manufactured such that they are similar to one another. A resistor manufactured by employing FinFET techniques is also described. The resistor can be manufactured with an effective length that is greater than a distance traversed along a substrate by the resistor.

    Abstract translation: 公开了FinFET半导体器件的各种实施例。 可以形成一对共用的源极，漏极和/或沟道的匹配电容器。 因此，可以制造每个电容器的电容特性使得它们彼此相似。 还描述了采用FinFET技术制造的电阻器。 电阻器可以制造成有效长度大于通过电阻器沿衬底穿过的距离。

    One Time Programmable Structure Using a Gate Last High-K Metal Gate Process
    8.
    发明申请
    One Time Programmable Structure Using a Gate Last High-K Metal Gate Process 有权
    使用栅极最后的高K金属栅极工艺的一次性可编程结构

    公开(公告)号：US20130082347A1

    公开(公告)日：2013-04-04

    申请号：US13249022

    申请日：2011-09-29

    Applicant: Xiangdong CHEN ,  Wei Xia

    Inventor： Xiangdong CHEN ,  Wei Xia

    IPC: H01L23/525 ,  H01L21/768

    CPC classification number: H01L23/5256 ,  H01L27/0629 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An eFuse structure having a first metal layer serving as a fuse with a gate including an undoped polysilicon (poly), a second metal layer and a high-K dielectric layer all formed on a silicon substrate with a Shallow Trench Isolation formation, and a process of fabricating same are provided. The eFuse structure enables use of low amounts of current to blow a fuse thus allowing the use of a smaller MOSFET.

    Abstract translation: 一种eFuse结构，其具有用作具有栅极的第一金属层，所述栅极包括未经掺杂的多晶硅（poly），第二金属层和高K电介质层，所述第一金属层全部用浅沟槽隔离层形成在硅衬底上，以及工艺 提供制造相同的。 eFuse结构使得能够使用少量的电流来熔断熔丝，从而允许使用更小的MOSFET。

    One-Time Programmable Device Having an LDMOS Structure and Related Method
    9.
    发明申请
    One-Time Programmable Device Having an LDMOS Structure and Related Method 有权
    具有LDMOS结构和相关方法的一次性可编程器件

    公开(公告)号：US20130082325A1

    公开(公告)日：2013-04-04

    申请号：US13252880

    申请日：2011-10-04

    Applicant: Akira Ito ,  Xiangdong Chen

    Inventor： Akira Ito ,  Xiangdong Chen

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/7816 ,  H01L21/76224 ,  H01L23/5252 ,  H01L27/088 ,  H01L27/11206 ,  H01L27/11226 ,  H01L27/1124 ,  H01L27/11246 ,  H01L27/11266 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.

    Abstract translation: 根据一个实施例，具有横向扩散的金属氧化物半导体（LDMOS）结构的一次性可编程（OTP）器件包括包括通过栅极电极和通过栅极电介质的通过栅极，以及包括编程门 电极和编程栅极电介质。 编程门通过LDMOS结构的漏极扩展区与通过栅极间隔开。 当用于将编程栅极电介质破裂的编程电压施加到编程栅电极时，LDMOS结构为通路提供保护。 一种用于制造这种OTP器件的方法包括形成漏极延伸区域，在漏极延伸区域的第一部分上制造栅极通孔，以及在漏极延伸区域的第二部分上制造编程栅极。

    Transistor with Reduced Channel Length Variation
    10.
    发明申请
    Transistor with Reduced Channel Length Variation 有权
    具有减少通道长度变化的晶体管

    公开(公告)号：US20130001687A1

    公开(公告)日：2013-01-03

    申请号：US13613864

    申请日：2012-09-13

    Applicant: Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

    Inventor： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

    IPC: H01L29/78

    CPC classification number: H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

    Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

    Abstract translation: 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

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