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    MOM capacitor having local interconnect metal plates and related method
    1.
    发明授权
    MOM capacitor having local interconnect metal plates and related method 有权
    具有局部互连金属板的MOM电容器及相关方法

    公开(公告)号：US08890288B2

    公开(公告)日：2014-11-18

    申请号：US13270452

    申请日：2011-10-11

    Applicant: Xiangdong Chen ,  Henry Kuo-Shun Chen

    Inventor： Xiangdong Chen ,  Henry Kuo-Shun Chen

    IPC: H01L21/02 ,  H01L23/522 ,  H01L27/06 ,  H01L49/02

    CPC classification number: H01L28/86 ,  H01L23/5223 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: According to one exemplary embodiment, a metal-oxide-metal (MOM) capacitor in a semiconductor die comprises a first plurality of capacitor plates and a second plurality of capacitor plates sharing a plane parallel to and below a plane of a first metallization layer of the semiconductor die. The MOM capacitor further comprises a local interlayer dielectric between the first plurality of capacitor plates and the second plurality of capacitor plates. The first and second plurality of capacitor plates are made from a local interconnect metal for connecting devices formed in a device layer of the semiconductor die situated below the first metallization layer.

    Abstract translation: 根据一个示例性实施例，半导体管芯中的金属氧化物金属（MOM）电容器包括第一多个电容器板和第二多个电容器板，第二多个电容器板共享平行于第一金属化层 半导体芯片。 MOM电容器还包括在第一多个电容器板和第二多个电容器板之间的局部层间电介质。 第一和第二多个电容器板由局部互连金属制成，用于连接形成在位于第一金属化层下方的半导体管芯的器件层中的器件。

    Method for fabricating a MOS transistor with reduced channel length variation and related structure
    2.
    发明申请
    Method for fabricating a MOS transistor with reduced channel length variation and related structure 有权
    具有减小沟道长度变化和相关结构的MOS晶体管的制造方法

    公开(公告)号：US20110089490A1

    公开(公告)日：2011-04-21

    申请号：US12589357

    申请日：2009-10-21

    Applicant: Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

    Inventor： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

    Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

    Abstract translation: 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

    One-time programmable memory cell
    3.
    发明申请
    One-time programmable memory cell 审中-公开
    一次性可编程存储单元

    公开(公告)号：US20100284210A1

    公开(公告)日：2010-11-11

    申请号：US12387573

    申请日：2009-05-05

    Applicant: Henry Kuo-Shun Chen ,  Xiangdong Chen ,  Wei Xia

    Inventor： Henry Kuo-Shun Chen ,  Xiangdong Chen ,  Wei Xia

    IPC: G11C17/00

    CPC classification number: G11C17/16

    Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a cell transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The cell transistor has a source, a gate, and a body shorted together. A programming operation causes a punchthrough to occur between the source and a drain of the cell transistor in response to a programming voltage on the bitline and the wordline. A channel length of the cell transistor is substantially less than a channel length of the access transistor. In one embodiment, the access transistor is an NFET while the cell transistor is a PFET. In another embodiment, the access transistor is an NFET and the cell transistor is also an NFET. Various embodiments result in a reduction of the required programming voltage.

    Abstract translation: 根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的单元晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。 单元晶体管具有源极，栅极和与之短接在一起的主体。 响应于位线和字线上的编程电压，编程操作导致在单元晶体管的源极和漏极之间发生穿透。 单元晶体管的沟道长度基本上小于存取晶体管的沟道长度。 在一个实施例中，存取晶体管是NFET，而单元晶体管是PFET。 在另一个实施例中，存取晶体管是NFET，单元晶体管也是NFET。 各种实施例导致所需编程电压的降低。

    Semiconductor device with increased breakdown voltage
    4.
    发明申请
    Semiconductor device with increased breakdown voltage 有权
    半导体器件具有增加的击穿电压

    公开(公告)号：US20080023760A1

    公开(公告)日：2008-01-31

    申请号：US11580961

    申请日：2006-10-16

    Applicant: Akira Ito ,  Henry Kuo-Shun Chen

    Inventor： Akira Ito ,  Henry Kuo-Shun Chen

    IPC: H01L29/76

    CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/7835

    Abstract: Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-Well regions adjacent to one another without an isolation region in between.

    Abstract translation: 优化使用常规互补金属氧化物硅（CMOS）逻辑铸造技术制造的金属氧化物硅场效应晶体管（MOSFET）器件的注入结构，以增加击穿电压。 用于优化注入结构的技术包括轻微注入栅极区域，使漏极区域从栅极区域移位，以及将P阱和N阱区域彼此相邻地注入，而不会在其间形成隔离区域。

    Method for Fabricating a MIM Capacitor Having a Local Interconnect Metal Electrode and Related Structure
    6.
    发明申请
    Method for Fabricating a MIM Capacitor Having a Local Interconnect Metal Electrode and Related Structure 有权
    具有局部互连金属电极和相关结构的MIM电容器的制造方法

    公开(公告)号：US20130082351A1

    公开(公告)日：2013-04-04

    申请号：US13248823

    申请日：2011-09-29

    Applicant: Xiangdong Chen ,  Henry Kuo-Shun Chen ,  Wei Xia ,  Bruce Chih-Chieh Shen

    Inventor： Xiangdong Chen ,  Henry Kuo-Shun Chen ,  Wei Xia ,  Bruce Chih-Chieh Shen

    IPC: H01L29/92 ,  H01L21/02

    CPC classification number: H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.

    Abstract translation: 根据一个示例性实施例，在半导体管芯中制造金属 - 绝缘体 - 金属（MIM）电容器的方法包括在位于半导体管芯的第一金属化层下方的器件层上形成底部电容器电极，并形成顶部电容器 形成在底部电容器电极上的层间势垒电介质上的电极。 顶部电容器电极由局部互连金属形成，用于连接器件层中形成的器件。 在一个实施例中，底部电容器电极由栅极金属形成。 该方法还可以包括在第一金属化层中和顶部电容器电极上形成金属板，并将金属板连接到底部电容器电极以提供增加的电容密度。

    Semiconductor device with increased breakdown voltage
    7.
    发明授权
    Semiconductor device with increased breakdown voltage 有权
    具有提高击穿电压的半导体器件

    公开(公告)号：US07855414B2

    公开(公告)日：2010-12-21

    申请号：US11580961

    申请日：2006-10-16

    Applicant: Akira Ito ,  Henry Kuo-Shun Chen

    Inventor： Akira Ito ,  Henry Kuo-Shun Chen

    IPC: H01L29/94 ,  H01L29/76

    CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/7835

    Abstract: Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.

    Abstract translation: 优化使用常规互补金属氧化物硅（CMOS）逻辑铸造技术制造的金属氧化物硅场效应晶体管（MOSFET）器件的注入结构，以增加击穿电压。 用于优化注入结构的技术包括轻微地注入栅极区域，使漏极区域从栅极区域移位，以及将P阱和N阱区域彼此相邻地注入，而不会在其间形成隔离区域。

    Method for selective gate halo implantation in a semiconductor die and related structure
    8.
    发明申请
    Method for selective gate halo implantation in a semiconductor die and related structure 有权
    半导体晶片中选择性栅晕注入的方法及相关结构

    公开(公告)号：US20100314691A1

    公开(公告)日：2010-12-16

    申请号：US12456065

    申请日：2009-06-10

    Applicant: Xiangdong Chen ,  Henry Kuo-Shun Chen ,  Kent Charles Oertle ,  Jennifer Chiao

    Inventor： Xiangdong Chen ,  Henry Kuo-Shun Chen ,  Kent Charles Oertle ,  Jennifer Chiao

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/66575 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/66537 ,  H01L29/78

    Abstract: According to one embodiment, a method for selective gate halo implantation includes forming at least one gate having a first orientation and at least one gate having a second orientation over a substrate. The method further includes performing a halo implant over the substrate. The first orientation allows a halo implanted area to be formed under the at least one gate having the first orientation and the second orientation prevents a halo implanted area from forming under the at least one gate having the second orientation. The halo implant is performed without forming a mask over the at least one gate having the first orientation or the at least one gate having the second orientation. The at least one gate having the first orientation can be used in a low voltage region of a substrate, while the at least one gate having the second orientation can be used in a high voltage region.

    Abstract translation: 根据一个实施例，用于选择性栅极晕晕注入的方法包括在衬底上形成具有第一取向的至少一个栅极和具有第二取向的至少一个栅极。 该方法还包括在衬底上执行晕轮植入。 第一取向允许在具有第一取向的至少一个栅极下方形成光晕注入区域，并且第二取向防止在具有第二取向的至少一个栅极下形成光晕注入区域。 在没有在具有第一取向的至少一个栅极或具有第二取向的至少一个栅极上形成掩模的情况下执行光晕注入。 具有第一取向的至少一个栅极可用于衬底的低电压区域，而具有第二取向的至少一个栅极可用于高电压区域。

    MIM capacitor having a local interconnect metal electrode and related structure
    9.
    发明授权
    MIM capacitor having a local interconnect metal electrode and related structure 有权
    具有局部互连金属电极和相关结构的MIM电容器

    公开(公告)号：US09041153B2

    公开(公告)日：2015-05-26

    申请号：US13248823

    申请日：2011-09-29

    Applicant: Xiangdong Chen ,  Henry Kuo-Shun Chen ,  Wei Xia ,  Bruce Chih-Chieh Shen

    Inventor： Xiangdong Chen ,  Henry Kuo-Shun Chen ,  Wei Xia ,  Bruce Chih-Chieh Shen

    IPC: H01L29/92 ,  H01L23/522 ,  H01L49/02

    CPC classification number: H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.

    Abstract translation: 根据一个示例性实施例，在半导体管芯中制造金属 - 绝缘体 - 金属（MIM）电容器的方法包括在位于半导体管芯的第一金属化层下方的器件层上形成底部电容器电极，并形成顶部电容器 形成在底部电容器电极上的层间势垒电介质上的电极。 顶部电容器电极由局部互连金属形成，用于连接器件层中形成的器件。 在一个实施例中，底部电容器电极由栅极金属形成。 该方法还可以包括在第一金属化层中和顶部电容器电极上形成金属板，并将金属板连接到底部电容器电极以提供增加的电容密度。

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